Now that the new common mvebu mbus API is available, lets use it on kirkwood as well. This includes a small change in the kirkwood EHCI driver. Making it more similar to the Linux driver from which it is ported.
Signed-off-by: Stefan Roese <[email protected]> --- arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 102 ++++++------------------------- arch/arm/include/asm/arch-kirkwood/cpu.h | 63 ++++++++++--------- arch/arm/include/asm/arch-kirkwood/soc.h | 16 ++--- arch/arm/mvebu-common/Makefile | 2 +- drivers/usb/host/ehci-marvell.c | 43 ++++--------- 5 files changed, 74 insertions(+), 152 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index c384565..6bfa4ec 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -13,101 +13,37 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -void reset_cpu(unsigned long ignored) -{ - struct kwcpu_registers *cpureg = - (struct kwcpu_registers *)KW_CPU_REG_BASE; - - writel(readl(&cpureg->rstoutn_mask) | (1 << 2), - &cpureg->rstoutn_mask); - writel(readl(&cpureg->sys_soft_rst) | 1, - &cpureg->sys_soft_rst); - while (1) ; -} - -/* - * Window Size - * Used with the Base register to set the address window size and location. - * Must be programmed from LSB to MSB as sequence of ones followed by - * sequence of zeros. The number of ones specifies the size of the window in - * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). - * NOTE: A value of 0x0 specifies 64-KByte size. - */ -unsigned int kw_winctrl_calcsize(unsigned int sizeval) -{ - int i; - unsigned int j = 0; - u32 val = sizeval >> 1; - - for (i = 0; val >= 0x10000; i++) { - j |= (1 << i); - val = val >> 1; - } - return (0x0000ffff & j); -} - -/* - * kw_config_adr_windows - Configure address Windows - * - * There are 8 address windows supported by Kirkwood Soc to addess different - * devices. Each window can be configured for size, BAR and remap addr - * Below configuration is standard for most of the cases - * - * If remap function not used, remap_lo must be set as base - * - * Reference Documentation: - * Mbus-L to Mbus Bridge Registers Configuration. - * (Sec 25.1 and 25.3 of Datasheet) - */ -int kw_config_adr_windows(void) -{ - struct kwwin_registers *winregs = - (struct kwwin_registers *)KW_CPU_WIN_BASE; - +static struct mbus_win windows[] = { /* Window 0: PCIE MEM address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE, - KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl); - - writel(KW_DEFADR_PCI_MEM, &winregs[0].base); - writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo); - writel(0x0, &winregs[0].remap_hi); + { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE, CPU_ATTR_PCIE_MEM }, /* Window 1: PCIE IO address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE, - KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl); - writel(KW_DEFADR_PCI_IO, &winregs[1].base); - writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo); - writel(0x0, &winregs[1].remap_hi); + { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE, CPU_ATTR_PCIE_IO }, /* Window 2: NAND Flash address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl); - writel(KW_DEFADR_NANDF, &winregs[2].base); - writel(KW_DEFADR_NANDF, &winregs[2].remap_lo); - writel(0x0, &winregs[2].remap_hi); + { DEFADR_NANDF, 128 << 20, CPU_TARGET_MEMORY, CPU_ATTR_NANDFLASH }, /* Window 3: SPI Flash address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl); - writel(KW_DEFADR_SPIF, &winregs[3].base); - writel(KW_DEFADR_SPIF, &winregs[3].remap_lo); - writel(0x0, &winregs[3].remap_hi); + { DEFADR_SPIF, 128 << 20, CPU_TARGET_MEMORY, CPU_ATTR_SPIFLASH }, /* Window 4: BOOT Memory address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl); - writel(KW_DEFADR_BOOTROM, &winregs[4].base); + { DEFADR_BOOTROM, 128 << 20, CPU_TARGET_MEMORY, CPU_ATTR_BOOTROM }, /* Window 5: Security SRAM address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM, - KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl); - writel(KW_DEFADR_SASRAM, &winregs[5].base); + { DEFADR_SASRAM, 64 << 10, CPU_TARGET_SASRAM, CPU_ATTR_SASRAM }, +}; - /* Window 6-7: Disabled */ - writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl); - writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl); +void reset_cpu(unsigned long ignored) +{ + struct kwcpu_registers *cpureg = + (struct kwcpu_registers *)KW_CPU_REG_BASE; - return 0; + writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + &cpureg->rstoutn_mask); + writel(readl(&cpureg->sys_soft_rst) | 1, + &cpureg->sys_soft_rst); + while (1) + ; } /* @@ -223,7 +159,7 @@ int arch_cpu_init(void) writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); invalidate_l2_cache(); - kw_config_adr_windows(); + mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index 926d347..cde978e 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -13,9 +13,6 @@ #ifndef __ASSEMBLY__ -#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ - | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) - #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c) @@ -34,41 +31,48 @@ enum memory_bank { }; enum kwcpu_winen { - KWCPU_WIN_DISABLE, - KWCPU_WIN_ENABLE + CPU_WIN_DISABLE, + CPU_WIN_ENABLE }; enum kwcpu_target { - KWCPU_TARGET_RESERVED, - KWCPU_TARGET_MEMORY, - KWCPU_TARGET_1RESERVED, - KWCPU_TARGET_SASRAM, - KWCPU_TARGET_PCIE + CPU_TARGET_RESERVED, + CPU_TARGET_MEMORY, + CPU_TARGET_1RESERVED, + CPU_TARGET_SASRAM, + CPU_TARGET_PCIE }; enum kwcpu_attrib { - KWCPU_ATTR_SASRAM = 0x01, - KWCPU_ATTR_DRAM_CS0 = 0x0e, - KWCPU_ATTR_DRAM_CS1 = 0x0d, - KWCPU_ATTR_DRAM_CS2 = 0x0b, - KWCPU_ATTR_DRAM_CS3 = 0x07, - KWCPU_ATTR_NANDFLASH = 0x2f, - KWCPU_ATTR_SPIFLASH = 0x1e, - KWCPU_ATTR_BOOTROM = 0x1d, - KWCPU_ATTR_PCIE_IO = 0xe0, - KWCPU_ATTR_PCIE_MEM = 0xe8 + CPU_ATTR_SASRAM = 0x01, + CPU_ATTR_DRAM_CS0 = 0x0e, + CPU_ATTR_DRAM_CS1 = 0x0d, + CPU_ATTR_DRAM_CS2 = 0x0b, + CPU_ATTR_DRAM_CS3 = 0x07, + CPU_ATTR_NANDFLASH = 0x2f, + CPU_ATTR_SPIFLASH = 0x1e, + CPU_ATTR_BOOTROM = 0x1d, + CPU_ATTR_PCIE_IO = 0xe0, + CPU_ATTR_PCIE_MEM = 0xe8 }; /* * Default Device Address MAP BAR values */ -#define KW_DEFADR_PCI_MEM 0x90000000 -#define KW_DEFADR_PCI_IO 0xC0000000 -#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 -#define KW_DEFADR_SASRAM 0xC8010000 -#define KW_DEFADR_NANDF 0xD8000000 -#define KW_DEFADR_SPIF 0xE8000000 -#define KW_DEFADR_BOOTROM 0xF8000000 +#define DEFADR_PCI_MEM 0x90000000 +#define DEFADR_PCI_IO 0xC0000000 +#define DEFADR_PCI_IO_REMAP 0xC0000000 +#define DEFADR_SASRAM 0xC8010000 +#define DEFADR_NANDF 0xD8000000 +#define DEFADR_SPIF 0xE8000000 +#define DEFADR_BOOTROM 0xF8000000 + +struct mbus_win { + u32 base; + u32 size; + u8 target; + u8 attr; +}; /* * read feroceon/sheeva core extra feature register @@ -97,7 +101,7 @@ static inline void writefr_extra_feature_reg(unsigned int val) * MBus-L to Mbus Bridge Registers * Ref: Datasheet sec:A.3 */ -struct kwwin_registers { +struct mvebu_win_registers { u32 ctrl; u32 base; u32 remap_lo; @@ -143,13 +147,12 @@ unsigned char get_random_hex(void); unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int kw_config_adr_windows(void); +int mvebu_mbus_probe(struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23, unsigned int mpp24_31, unsigned int mpp32_39, unsigned int mpp40_47, unsigned int mpp48_55); -unsigned int kw_winctrl_calcsize(unsigned int sizeval); #endif /* __ASSEMBLY__ */ #endif /* _KWCPU_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/include/asm/arch-kirkwood/soc.h index 75120b1..41a6f85 100644 --- a/arch/arm/include/asm/arch-kirkwood/soc.h +++ b/arch/arm/include/asm/arch-kirkwood/soc.h @@ -32,7 +32,7 @@ #define KW_RTC_BASE (KW_REGISTER(0x10300)) #define KW_NANDF_BASE (KW_REGISTER(0x10418)) #define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) -#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) +#define MVEBU_CPU_WIN_BASE (KW_REGISTER(0x20000)) #define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) #define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) @@ -52,15 +52,15 @@ /* Kirkwood USB Host controller */ #define MVUSB0_BASE KW_USB20_BASE -#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 -#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 -#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 -#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 +#define MVUSB0_CPU_ATTR_DRAM_CS0 CPU_ATTR_DRAM_CS0 +#define MVUSB0_CPU_ATTR_DRAM_CS1 CPU_ATTR_DRAM_CS1 +#define MVUSB0_CPU_ATTR_DRAM_CS2 CPU_ATTR_DRAM_CS2 +#define MVUSB0_CPU_ATTR_DRAM_CS3 CPU_ATTR_DRAM_CS3 /* Kirkwood CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA -#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE -#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE +#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA +#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE +#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE #if defined (CONFIG_KW88F6281) #include <asm/arch/kw88f6281.h> diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile index 9dcab69..ed75ffb 100644 --- a/arch/arm/mvebu-common/Makefile +++ b/arch/arm/mvebu-common/Makefile @@ -8,5 +8,5 @@ obj-y = dram.o obj-y += gpio.o -obj-$(CONFIG_ARMADA_XP) += mbus.o +obj-y += mbus.o obj-y += timer.o diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 1a5fd6e..2d75031 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -11,6 +11,7 @@ #include <usb.h> #include "ehci.h" #include <asm/arch/cpu.h> +#include <linux/mbus.h> #if defined(CONFIG_KIRKWOOD) #include <asm/arch/soc.h> @@ -32,41 +33,23 @@ DECLARE_GLOBAL_DATA_PTR; */ static void usb_brg_adrdec_setup(void) { + const struct mbus_dram_target_info *dram; int i; - u32 size, base, attrib; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + dram = mvebu_mbus_dram_info(); - /* Enable DRAM bank */ - switch (i) { - case 0: - attrib = MVUSB0_CPU_ATTR_DRAM_CS0; - break; - case 1: - attrib = MVUSB0_CPU_ATTR_DRAM_CS1; - break; - case 2: - attrib = MVUSB0_CPU_ATTR_DRAM_CS2; - break; - case 3: - attrib = MVUSB0_CPU_ATTR_DRAM_CS3; - break; - default: - /* invalide bank, disable access */ - attrib = 0; - break; - } + for (i = 0; i < 4; i++) { + wrl(USB_WINDOW_CTRL(i), 0); + wrl(USB_WINDOW_BASE(i), 0); + } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; - if ((size) && (attrib)) - wrl(USB_WINDOW_CTRL(i), - MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, - attrib, MVCPU_WIN_ENABLE)); - else - wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE); + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; - wrl(USB_WINDOW_BASE(i), base); + wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1); + wrl(USB_WINDOW_BASE(i), cs->base); } } -- 2.0.1 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
