On 07/03/2014 12:24 AM, Alison Wang wrote: > The QorIQ LS1 family is built on Layerscape architecture, > the industry's first software-aware, core-agnostic networking > architecture to offer unprecedented efficiency and scale. > > Freescale LS102xA is a set of SoCs combines two ARM > Cortex-A7 cores that have been optimized for high > reliability and pack the highest level of integration > available for sub-3 W embedded communications processors > with Layerscape architecture and with a comprehensive > enablement model focused on ease of programmability. > > Signed-off-by: Alison Wang <[email protected]> > Signed-off-by: Jason Jin <[email protected]> > Signed-off-by: Jingchang Lu <[email protected]> > Signed-off-by: Prabhakar Kushwaha <[email protected]> > --- > Change log: > v2: Add serdes support. > Update DDR frequency and data rate information. > Fix overflow condition error for the timer. >
Albert, As you can see, Freescale starts to make ARM core SoCs on QorIQ product line. As previously discussed, I will maintain fsl-qoriq repository to host these patches. Beside ARMv8, I am new to ARM cores. To start, I would like to solicit your comments/ack for this series. It will be helpful if you can share how ARM maintainers do the daily jobs like sending notice, pull requests, etc. York _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
