Hello Lokesh,
On 28-07-14 06:08, Lokesh Vutla wrote:
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so enabling this gpio for all the
boards, as it is unaffected.
Signed-off-by: Lokesh Vutla <[email protected]>
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 6 ++++++
arch/arm/include/asm/arch-omap5/gpio.h | 12 ++++++++++++
arch/arm/include/asm/arch-omap5/sys_proto.h | 1 +
board/ti/dra7xx/evm.c | 21 +++++++++++++++++++++
board/ti/dra7xx/mux_data.h | 1 +
5 files changed, 41 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 71c0cc8..74ebf41 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1307,6 +1307,10 @@ static void do_bug0039_workaround(u32 base)
__raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
}
+void __weak ddr_regulator_enable(void)
+{
+}
+
ddr_regulator_enable misses a prototype (or I fail to locate it).
Regards,
Jeroen
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