On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov <[email protected]> wrote: > Bit 16 in mapsr register is in a reserved field. Don't write to it. > > Cc: Stefano Babic <[email protected]> > Cc: Tim Harvey <[email protected]> > Signed-off-by: Nikita Kiryanov <[email protected]> > --- > arch/arm/cpu/armv7/mx6/ddr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c > index af91314..70ce38f 100644 > --- a/arch/arm/cpu/armv7/mx6/ddr.c > +++ b/arch/arm/cpu/armv7/mx6/ddr.c > @@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, > 1 << 6 | /* BOTH_CS_PD */ > (tcksrx & 0x7) << 3 | > (tcksre & 0x7); > - mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */ > + mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ > > /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ > val = 0xa1390003; > -- > 1.9.1 >
Nikita, This makes sense per the reference manual, but does not agree with the i.Mx6DQSDL DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I'm curious if you found any other explanation of this or anything else that makes you feel the spreadsheet is in error (vs the RM's). I've asked our Freescale FAE to clarify. Regards, Tim _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
