Hi Tim, On Fri, Aug 8, 2014 at 2:57 AM, Tim Harvey <[email protected]> wrote: > According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable > for SS function) must remain deasserted until the reference clock is running > at the appropriate frequency. > > Without this patch we find a high link failure rate (>5%) on certain > IMX6 boards at various temperatures. > > Signed-off-by: Tim Harvey <[email protected]>
Looks good, thanks. Reviewed-by: Fabio Estevam <[email protected]> Also Cc Richard and Rogerio in case they have any comment. > --- > drivers/pci/pcie_imx.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c > index c48737e..a3982c4 100644 > --- a/drivers/pci/pcie_imx.c > +++ b/drivers/pci/pcie_imx.c > @@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void) > > imx6_pcie_toggle_power(); > > - /* Enable PCIe */ > - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); > - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); > - > enable_pcie_clock(); > > /* > @@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void) > */ > mdelay(50); > > + /* Enable PCIe */ > + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); > + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); > + > imx6_pcie_toggle_reset(); > > return 0; _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
