On 08/25/2014 12:31 PM, Simon Glass wrote:
Hi,
On 11 August 2014 09:23, Simon Glass <[email protected]> wrote:
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <[email protected]>
Any comments on this one please?
Tom, can you please review this patch/series? Thanks.
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