Hi Marek,

On 8/29/2014 12:30 PM, Marek Vasut wrote:
+static struct mx6_mmdc_calibration novena_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0         = 0x00420048,
+       .p0_mpwldectrl1         = 0x006f0059,
+       .p1_mpwldectrl0         = 0x005a0104,
+       .p1_mpwldectrl1         = 0x01070113,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0           = 0x437c040b,
+       .p0_mpdgctrl1           = 0x0413040e,
+       .p1_mpdgctrl0           = 0x444f0446,
+       .p1_mpdgctrl1           = 0x044d0422,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl           = 0x4c424249,
+       .p1_mprddlctl           = 0x4e48414f,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl           = 0x42414641,
+       .p1_mpwrdlctl           = 0x46374b43,
+};
I think these values should be result of MMDC calibration. If they're hardcoded, some SO-DIMM modules will work, some won't.

+static struct mx6_ddr_sysinfo novena_ddr_info = {
+       /* Width of data bus: 0=16, 1=32, 2=64 */
+       .dsize          = 2,
+       /* Config for full 4GB range so that get_mem_size() works */
+       .cs_density     = 32,   /* 32Gb per CS */
+       /* Single chip select */
+       .ncs            = 1,
+       .cs1_mirror     = 0,
+       .rtt_wr         = 1,    /* RTT_Wr = RZQ/4 */
+       .rtt_nom        = 2,    /* RTT_Nom = RZQ/2 */
+       .walat          = 3,    /* Write additional latency */
+       .ralat          = 7,    /* Read additional latency */
+       .mif3_mode      = 3,    /* Command prediction working mode */
+       .bi_on          = 1,    /* Bank interleaving enabled */
+       .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
+       .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
+};
ncs is hard-coded to 1, while there are available SO-DIMMS on the market which have 2 ranks. Novena is supposed to handle memory modules up to 4GiB, which means that there's a high chance to have 2-rank module installed.

+
+static struct mx6_ddr3_cfg elpida_4gib_1600 = {
+       .mem_speed      = 1600,
+       .density        = 4,
+       .width          = 64,
+       .banks          = 8,
+       .rowaddr        = 16,
+       .coladdr        = 10,
+       .pagesz         = 2,
+       .trcd           = 1300,
+       .trcmin         = 4900,
+       .trasmin        = 3590,
+};
Again, this should be read from SPD mem, not hard-coded.

And finally - thank you so much for putting the efforts to add support for the Novena open-source board!

Kind regards,
Nikolay
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