On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote: > From: Hans de Goede <[email protected]> > > The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO > or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it. SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad. I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing) If we still need SUNXI_GPIO_BANKS after that then it would be the sum of those two. > Signed-off-by: Hans de Goede <[email protected]> > [[email protected]: expanded commit message] > [[email protected]: add pin bank M and expand comments] > Signed-off-by: Chen-Yu Tsai <[email protected]> > --- > arch/arm/include/asm/arch-sunxi/gpio.h | 25 +++++++++++++++++++++++-- > 1 file changed, 23 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h > b/arch/arm/include/asm/arch-sunxi/gpio.h > index b94ec4d..bbe815a 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -10,6 +10,7 @@ > #define _SUNXI_GPIO_H > > #include <linux/types.h> > +#include <asm/arch/cpu.h> > > /* > * sunxi has 9 banks of gpio, they are: > @@ -29,6 +30,19 @@ > #define SUNXI_GPIO_I 8 > #define SUNXI_GPIO_BANKS 9 > > +/* > + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) > + * at a different register offset. > + * > + * sun6i has 2 banks: > + * PL0 - PL8 | PM0 - PM7 > + * > + * sun8i has 1 bank: > + * PL0 - PL11 > + */ > +#define SUNXI_GPIO_L 9 > +#define SUNXI_GPIO_M 10 > + > struct sunxi_gpio { > u32 cfg[4]; > u32 dat; > @@ -50,8 +64,9 @@ struct sunxi_gpio_reg { > struct sunxi_gpio_int gpio_int; > }; > > -#define BANK_TO_GPIO(bank) \ > - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] > +#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_BANKS) ? \ > + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ > + &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - > SUNXI_GPIO_BANKS]) > > #define GPIO_BANK(pin) ((pin) >> 5) > #define GPIO_NUM(pin) ((pin) & 0x1f) > @@ -75,6 +90,8 @@ struct sunxi_gpio_reg { > #define SUNXI_GPIO_G_NR 32 > #define SUNXI_GPIO_H_NR 32 > #define SUNXI_GPIO_I_NR 32 > +#define SUNXI_GPIO_L_NR 32 > +#define SUNXI_GPIO_M_NR 32 > > #define SUNXI_GPIO_NEXT(__gpio) \ > ((__gpio##_START) + (__gpio##_NR) + 0) > @@ -89,6 +106,8 @@ enum sunxi_gpio_number { > SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), > SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), > SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), > + SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I), > + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), > }; > > /* SUNXI GPIO number definitions */ > @@ -101,6 +120,8 @@ enum sunxi_gpio_number { > #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) > #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) > #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) > +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) > +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) > > /* GPIO pin function config */ > #define SUNXI_GPIO_INPUT 0 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
