Add short documentation-alike note on how to use the Altera SPI driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V.
Signed-off-by: Marek Vasut <[email protected]> Cc: Chin Liang See <[email protected]> Cc: Dinh Nguyen <[email protected]> Cc: Albert Aribaud <[email protected]> Cc: Tom Rini <[email protected]> Cc: Wolfgang Denk <[email protected]> Cc: Pavel Machek <[email protected]> Cc: Jagannadha Sutradharudu Teki <[email protected]> --- drivers/spi/altera_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 3065e96..0566e4f 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -4,6 +4,14 @@ * based on bfin_spi.c * Copyright (c) 2005-2008 Analog Devices Inc. * Copyright (C) 2010 Thomas Chou <[email protected]> + * Copyright (C) 2014 Marek Vasut <[email protected]> + * + * SoCFPGA EPCS/EPCQx1 mini howto: + * - Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild + * - The controller base address is the "Base" in QSys + 0x400 + * - Set MSEL[4:0]=10010 (AS Standard) + * - Load the bitstream into FPGA, enable bridges + * - Only then will the driver work * * SPDX-License-Identifier: GPL-2.0+ */ -- 2.1.1 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
