Workaround of Errata A-008044 was implemented without errata number and it is
enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0.
So put errata number and make it conditional.
Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com>
---
Changes for v2:
- updated CONFIG_A08044_WORKAROUND to CONFIG_A008044_WORKAROUND
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 ++-
board/freescale/t104xrdb/spl.c | 22 ++++++++++++++--------
2 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index b670f30..ba08330 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -310,7 +310,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
defined(CONFIG_A008044_WORKAROUND)
- puts("Work-around for Erratum A-008044 enabled\n");
+ if (IS_SVR_REV(svr, 1, 0))
+ puts("Work-around for Erratum A-008044 enabled\n");
#endif
return 0;
}
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 75d9d9c..e394b12 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -36,18 +36,24 @@ void board_init_f(ulong bootflag)
u32 plat_ratio, sys_clk, uart_clk;
#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
u32 porsr1, pinctl;
+ u32 svr = get_svr();
#endif
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
- /*
- * There is T1040 SoC issue where NOR, FPGA are inaccessible during
- * NAND boot because IFC signals > IFC_AD7 are not enabled.
- * This workaround changes RCW source to make all signals enabled.
- */
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+ if (IS_SVR_REV(svr, 1, 0)) {
+ /*
+ * There is T1040 SoC issue where NOR, FPGA are inaccessible
+ * during NAND boot because IFC signals > IFC_AD7 are not
+ * enabled. This workaround changes RCW source to make all
+ * signals enabled.
+ */
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
+ | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+ pinctl);
+ }
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
--
1.9.1
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