On 31 October 2014 02:55, Akshay Saraswat <[email protected]> wrote: > From: Alim Akhtar <[email protected]> > > As per Exynos5800 UM ver 0.00 section 17.13.2.1 > CONCONTROL register bit 3 [update_mode], Exynos5800 does not > support the PHY initiated update. And it is recommanded to > set this field to 1'b1 during initialization. This patch sets this bit. > Applying MC-initiated mode makes DDL tracking ON, that helps in > compensate MIF voltage variation. > > Signed-off-by: Alim Akhtar <[email protected]> > Signed-off-by: Doug Anderson <[email protected]> > Signed-off-by: Akshay Saraswat <[email protected]> > --- > Changes since v2: > - Rebased this patch > > Changes since v1: > - Rebased this patch > > arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 19 +++++++++++++++++++ > arch/arm/include/asm/arch-exynos/dmc.h | 1 + > 2 files changed, 20 insertions(+) >
Acked-by: Simon Glass <[email protected]> Tested on Pi: Tested-by: Simon Glass <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
