On 31 December 2014 at 01:05, Bin Meng <bmeng...@gmail.com> wrote: > The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton > 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per > Open Firmware PCI bus bindings. > > Also a comment block is added for the 'stdout-path' property in the > chosen node, mentioning that by default the legacy superio serial > port (io addr 0x3f8) is still used on Crown Bay as the console port. > > Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Simon Glass <s...@chromium.org> > > --- > > Changes in v4: > - Add , after pciclass in the pci compatible string per spec > - Drop the first 3 patches which are already applied > > Changes in v3: None > Changes in v2: > - New patch to add pci devices in crownbay.dts > - Drop v1 patch: Add an API for finding pci devices in the early phase > - Drop v1 patch: Support PCI UART in the x86_serial driver > - Drop v1 patch: Add PCI UART related defines in crownbay.h > > arch/x86/dts/crownbay.dts | 81 > +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 81 insertions(+) _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
