FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks.
Signed-off-by: York Sun <[email protected]> --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 1 + arch/arm/cpu/armv8/fsl-lsch3/speed.c | 16 ++++++++++++++-- arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 3 +++ arch/arm/include/asm/global_data.h | 3 +++ 4 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 2aaac01..42cee65 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -367,6 +367,7 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); + printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); puts("\n"); return 0; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c index dc4a34b..72cd999 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_systembus = sysclk; #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; #else sys_info->freq_ddrbus = sysclk; + sys_info->freq_ddrbus2 = sysclk; #endif sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> @@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; + sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { /* @@ -129,7 +134,7 @@ int get_clocks(void) gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus; gd->mem_clk = sys_info.freq_ddrbus; - + gd->arch.mem2_clk = sys_info.freq_ddrbus2; #if defined(CONFIG_FSL_ESDHC) gd->arch.sdhc_clk = gd->bus_clk / 2; #endif /* defined(CONFIG_FSL_ESDHC) */ @@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy) * get_ddr_freq * return ddr bus freq in Hz *********************************************/ -ulong get_ddr_freq(ulong dummy) +ulong get_ddr_freq(ulong ctrl_num) { if (!gd->mem_clk) get_clocks(); + /* + * DDR controller 0 & 1 are on memory complex 0 + * DDR controler 2 is on memory complext 1 + */ + if (ctrl_num >= 2) + return gd->arch.mem2_clk; + return gd->mem_clk; } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index ee1d651..dd11ef7 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -15,6 +15,7 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; unsigned long freq_ddrbus; + unsigned long freq_ddrbus2; unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN @@ -60,6 +61,8 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f u8 res_180[0x200-0x180]; u32 scratchrw[32]; /* Scratch Read/Write */ u8 res_280[0x300-0x280]; diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 438f128..bb24f33 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -48,6 +48,9 @@ struct arch_global_data { #ifdef CONFIG_OMAP struct omap_boot_parameters omap_boot_params; #endif +#ifdef CONFIG_FSL_LSCH3 + unsigned long mem2_clk; +#endif }; #include <asm-generic/global_data.h> -- 1.7.9.5 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
