Hi Pantelis, On Mon, Jan 19, 2015 at 10:47 AM, Pantelis Antoniou <pantelis.anton...@gmail.com> wrote: > > Hi Volodymyr, > > > On Jan 14, 2015, at 22:46 , Volodymyr Riazantsev > > <volodymyr.riazant...@globallogic.com> wrote: > > > > Add support of the DDR mode for eSDHC driver. > > Enable it for i.MX6 SoC family only. > > > > Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116 > > Signed-off-by: Volodymyr Riazantsev <volodymyr.riazant...@globallogic.com> > > --- > > drivers/mmc/fsl_esdhc.c | 8 ++++++-- > > include/fsl_esdhc.h | 1 + > > 2 files changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > > index c55eb28..abec45f 100644 > > --- a/drivers/mmc/fsl_esdhc.c > > +++ b/drivers/mmc/fsl_esdhc.c > > @@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, > > struct mmc_data *data) > > esdhc_write32(®s->cmdarg, cmd->cmdarg); > > #if defined(CONFIG_FSL_USDHC) > > esdhc_write32(®s->mixctrl, > > - (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); > > + (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) > > + | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); > > esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); > > #else > > esdhc_write32(®s->xfertyp, xfertyp); > > @@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) > > if ((sdhc_clk / (div * pre_div)) <= clock) > > break; > > > > - pre_div >>= 1; > > + pre_div >>= mmc->ddr_mode ? 2 : 1; > > div -= 1; > > > > clk = (pre_div << 8) | (div << 4); > > @@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct > > fsl_esdhc_cfg *cfg) > > } > > > > cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; > > +#ifdef CONFIG_MX6 > > + cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; > > +#endif > > > > if (cfg->max_bus_width > 0) { > > if (cfg->max_bus_width < 8) > > diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h > > index c1b6648..313fa1e 100644 > > --- a/include/fsl_esdhc.h > > +++ b/include/fsl_esdhc.h > > @@ -108,6 +108,7 @@ > > #define XFERTYP_RSPTYP_48_BUSY 0x00030000 > > #define XFERTYP_MSBSEL 0x00000020 > > #define XFERTYP_DTDSEL 0x00000010 > > +#define XFERTYP_DDREN 0x00000008 > > #define XFERTYP_AC12EN 0x00000004 > > #define XFERTYP_BCEN 0x00000002 > > #define XFERTYP_DMAEN 0x00000001 > > -- > > 2.2.0 > > The patch is OK, but I don’t like the use of CONFIG_MX6 for enabling it. > The meaning is that the MMC IP block in MX6 supports DDR mode, so make it a > quirk > that’s enabled for MX6. > > Subsequent SoCs might use the same mode, so I don’t like having to do endless > defines > of SoC families. > > Please rework. > > Regards > > — Pantelis
Thank you for the comments, I've reworked patch for get ability to enable this feature via separate configuration flag. I put that flag into common mx6 header, otherwise we have to enable it for each separate mx6 board. I didn't found way to run-time check for this feature on the initialization path. Best regards, Volodymyr. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot