On 19 January 2015 at 22:16, Simon Glass <s...@chromium.org> wrote: > Correct the SPI flash compatible string, add an alias and specify the > position of the MRC cache, used to store SDRAM training settings for the > Memory Reference Code. > > Signed-off-by: Simon Glass <s...@chromium.org> > --- > > Changes in v3: > - Drop accidental creation of link.dts due to bad rebase > > Changes in v2: > - Make changes to chromebook_link.dts since link.dts is gone > - Use intel,ich-spi as the compatible string > > arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-)
Applied to u-boot-x86. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
