Hi, 2015-02-14 7:06 GMT+09:00 Vladimir Barinov <[email protected]>: > Porter is an entry level development board based on R-Car M2 SoC (R8A7791) > > This commit supports the following peripherals: > - SCIF, I2C, Ethernet, QSPI, SD, USB Host > > Signed-off-by: Vladimir Barinov <[email protected]>
Applied, thanks. Nobuhiro > --- > arch/arm/cpu/armv7/rmobile/Kconfig | 6 +- > board/renesas/porter/Kconfig | 12 + > board/renesas/porter/MAINTAINERS | 6 + > board/renesas/porter/Makefile | 10 + > board/renesas/porter/porter.c | 228 +++++++ > board/renesas/porter/qos.c | 1312 > ++++++++++++++++++++++++++++++++++++ > board/renesas/porter/qos.h | 13 + > configs/porter_defconfig | 6 + > include/configs/porter.h | 112 +++ > 9 files changed, 1704 insertions(+), 1 deletion(-) > create mode 100644 board/renesas/porter/Kconfig > create mode 100644 board/renesas/porter/MAINTAINERS > create mode 100644 board/renesas/porter/Makefile > create mode 100644 board/renesas/porter/porter.c > create mode 100644 board/renesas/porter/qos.c > create mode 100644 board/renesas/porter/qos.h > create mode 100644 configs/porter_defconfig > create mode 100644 include/configs/porter.h > > diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig > b/arch/arm/cpu/armv7/rmobile/Kconfig > index 3586650..2b333a3 100644 > --- a/arch/arm/cpu/armv7/rmobile/Kconfig > +++ b/arch/arm/cpu/armv7/rmobile/Kconfig > @@ -24,6 +24,9 @@ config TARGET_ALT > config TARGET_SILK > bool "Silk board" > > +config TARGET_PORTER > + bool "Porter board" > + > endchoice > > config SYS_SOC > @@ -31,7 +34,7 @@ config SYS_SOC > > config RMOBILE_EXTRAM_BOOT > bool "Enable boot from RAM" > - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK > + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || > TARGET_PORTER || TARGET_SILK > default n > > source "board/atmark-techno/armadillo-800eva/Kconfig" > @@ -41,5 +44,6 @@ source "board/renesas/lager/Kconfig" > source "board/kmc/kzm9g/Kconfig" > source "board/renesas/alt/Kconfig" > source "board/renesas/silk/Kconfig" > +source "board/renesas/porter/Kconfig" > > endif > diff --git a/board/renesas/porter/Kconfig b/board/renesas/porter/Kconfig > new file mode 100644 > index 0000000..a6f621b > --- /dev/null > +++ b/board/renesas/porter/Kconfig > @@ -0,0 +1,12 @@ > +if TARGET_PORTER > + > +config SYS_BOARD > + default "porter" > + > +config SYS_VENDOR > + default "renesas" > + > +config SYS_CONFIG_NAME > + default "porter" > + > +endif > diff --git a/board/renesas/porter/MAINTAINERS > b/board/renesas/porter/MAINTAINERS > new file mode 100644 > index 0000000..1dc6a1c > --- /dev/null > +++ b/board/renesas/porter/MAINTAINERS > @@ -0,0 +1,6 @@ > +PORTER BOARD > +M: Cogent Embedded, Inc. <[email protected]> > +S: Maintained > +F: board/renesas/porter/ > +F: include/configs/porter.h > +F: configs/porter_defconfig > diff --git a/board/renesas/porter/Makefile b/board/renesas/porter/Makefile > new file mode 100644 > index 0000000..dbf32e9 > --- /dev/null > +++ b/board/renesas/porter/Makefile > @@ -0,0 +1,10 @@ > +# > +# board/renesas/porter/Makefile > +# > +# Copyright (C) 2015 Renesas Electronics Corporation > +# Copyright (C) 2015 Cogent Embedded, Inc. > +# > +# SPDX-License-Identifier: GPL-2.0 > +# > + > +obj-y := porter.o qos.o ../rcar-gen2-common/common.o > diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c > new file mode 100644 > index 0000000..b5378de > --- /dev/null > +++ b/board/renesas/porter/porter.c > @@ -0,0 +1,228 @@ > +/* > + * board/renesas/porter/porter.c > + * > + * Copyright (C) 2015 Renesas Electronics Corporation > + * Copyright (C) 2015 Cogent Embedded, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#include <common.h> > +#include <malloc.h> > +#include <dm.h> > +#include <dm/platform_data/serial_sh.h> > +#include <asm/processor.h> > +#include <asm/mach-types.h> > +#include <asm/io.h> > +#include <asm/errno.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/gpio.h> > +#include <asm/arch/rmobile.h> > +#include <asm/arch/rcar-mstp.h> > +#include <asm/arch/sh_sdhi.h> > +#include <netdev.h> > +#include <miiphy.h> > +#include <i2c.h> > +#include <div64.h> > +#include "qos.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define CLK2MHZ(clk) (clk / 1000 / 1000) > +void s_init(void) > +{ > + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; > + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; > + u32 stc; > + > + /* Watchdog init */ > + writel(0xA5A5A500, &rwdt->rwtcsra); > + writel(0xA5A5A500, &swdt->swtcsra); > + > + /* CPU frequency setting. Set to 1.5GHz */ > + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; > + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); > + > + /* QoS */ > + qos_init(); > +} > + > +#define TMU0_MSTP125 (1 << 25) > +#define SDHI0_MSTP314 (1 << 14) > +#define SDHI2_MSTP311 (1 << 11) > +#define SCIF0_MSTP721 (1 << 21) > +#define ETHER_MSTP813 (1 << 13) > + > +#define SD2CKCR 0xE615026C > +#define SD_97500KHZ 0x7 > + > +int board_early_init_f(void) > +{ > + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); > + > + /* SCIF0 */ > + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); > + > + /* ETHER */ > + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); > + > + /* SDHI */ > + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311); > + > + /* > + * SD0 clock is set to 97.5MHz by default. > + * Set SD2 to the 97.5MHz as well. > + */ > + writel(SD_97500KHZ, SD2CKCR); > + > + return 0; > +} > + > +/* LSI pin pull-up control */ > +#define PUPR5 0xe6060114 > +#define PUPR5_ETH 0x3FFC0000 > +#define PUPR5_ETH_MAGIC (1 << 27) > +int board_init(void) > +{ > + /* adress of boot parameters */ > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; > + > + /* Init PFC controller */ > + r8a7791_pinmux_init(); > + > + /* Ether Enable */ > + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); > + gpio_request(GPIO_FN_ETH_RX_ER, NULL); > + gpio_request(GPIO_FN_ETH_RXD0, NULL); > + gpio_request(GPIO_FN_ETH_RXD1, NULL); > + gpio_request(GPIO_FN_ETH_LINK, NULL); > + gpio_request(GPIO_FN_ETH_REFCLK, NULL); > + gpio_request(GPIO_FN_ETH_MDIO, NULL); > + gpio_request(GPIO_FN_ETH_TXD1, NULL); > + gpio_request(GPIO_FN_ETH_TX_EN, NULL); > + gpio_request(GPIO_FN_ETH_TXD0, NULL); > + gpio_request(GPIO_FN_ETH_MDC, NULL); > + gpio_request(GPIO_FN_IRQ0, NULL); > + > + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); > + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ > + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); > + > + gpio_direction_output(GPIO_GP_5_22, 0); > + mdelay(20); > + gpio_set_value(GPIO_GP_5_22, 1); > + udelay(1); > + > + return 0; > +} > + > +#define CXR24 0xEE7003C0 /* MAC address high register */ > +#define CXR25 0xEE7003C8 /* MAC address low register */ > +int board_eth_init(bd_t *bis) > +{ > +#ifdef CONFIG_SH_ETHER > + int ret = -ENODEV; > + u32 val; > + unsigned char enetaddr[6]; > + > + ret = sh_eth_initialize(bis); > + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) > + return ret; > + > + /* Set Mac address */ > + val = enetaddr[0] << 24 | enetaddr[1] << 16 | > + enetaddr[2] << 8 | enetaddr[3]; > + writel(val, CXR24); > + > + val = enetaddr[4] << 8 | enetaddr[5]; > + writel(val, CXR25); > + > + return ret; > +#else > + return 0; > +#endif > +} > + > +int board_mmc_init(bd_t *bis) > +{ > + int ret = -ENODEV; > + > +#ifdef CONFIG_SH_SDHI > + gpio_request(GPIO_FN_SD0_DATA0, NULL); > + gpio_request(GPIO_FN_SD0_DATA1, NULL); > + gpio_request(GPIO_FN_SD0_DATA2, NULL); > + gpio_request(GPIO_FN_SD0_DATA3, NULL); > + gpio_request(GPIO_FN_SD0_CLK, NULL); > + gpio_request(GPIO_FN_SD0_CMD, NULL); > + gpio_request(GPIO_FN_SD0_CD, NULL); > + gpio_request(GPIO_FN_SD2_DATA0, NULL); > + gpio_request(GPIO_FN_SD2_DATA1, NULL); > + gpio_request(GPIO_FN_SD2_DATA2, NULL); > + gpio_request(GPIO_FN_SD2_DATA3, NULL); > + gpio_request(GPIO_FN_SD2_CLK, NULL); > + gpio_request(GPIO_FN_SD2_CMD, NULL); > + gpio_request(GPIO_FN_SD2_CD, NULL); > + > + /* SDHI 0 */ > + gpio_request(GPIO_GP_2_12, NULL); > + gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ > + > + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, > + SH_SDHI_QUIRK_16BIT_BUF); > + if (ret) > + return ret; > + > + /* SDHI 2 */ > + gpio_request(GPIO_GP_2_26, NULL); > + gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ > + > + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); > +#endif > + return ret; > +} > + > +int dram_init(void) > +{ > + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; > + > + return 0; > +} > + > +/* porter has KSZ8041RNLI */ > +#define PHY_CONTROL1 0x1E > +#define PHY_LED_MODE 0xC0000 > +#define PHY_LED_MODE_ACK 0x4000 > +int board_phy_config(struct phy_device *phydev) > +{ > + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); > + ret &= ~PHY_LED_MODE; > + ret |= PHY_LED_MODE_ACK; > + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); > + > + return 0; > +} > + > +const struct rmobile_sysinfo sysinfo = { > + CONFIG_RMOBILE_BOARD_STRING > +}; > + > +void reset_cpu(ulong addr) > +{ > + u8 val; > + > + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ > + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); > + val |= 0x02; > + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); > +} > + > +static const struct sh_serial_platdata serial_platdata = { > + .base = SCIF0_BASE, > + .type = PORT_SCIF, > + .clk = CONFIG_P_CLK_FREQ, > +}; > + > +U_BOOT_DEVICE(porter_serials) = { > + .name = "serial_sh", > + .platdata = &serial_platdata, > +}; > diff --git a/board/renesas/porter/qos.c b/board/renesas/porter/qos.c > new file mode 100644 > index 0000000..491d1ba > --- /dev/null > +++ b/board/renesas/porter/qos.c > @@ -0,0 +1,1312 @@ > +/* > + * board/renesas/porter/qos.c > + * > + * Copyright (C) 2015 Renesas Electronics Corporation > + * Copyright (C) 2015 Cogent Embedded, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + * > + */ > + > +#include <common.h> > +#include <asm/processor.h> > +#include <asm/mach-types.h> > +#include <asm/io.h> > +#include <asm/arch/rmobile.h> > + > +/* QoS version 0.240 for ES1 and version 0.334 for ES2 */ > +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) > +enum { > + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, > + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, > + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, > + DBSC3_15, > + DBSC3_NR, > +}; > + > +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { > + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, > + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, > + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, > + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, > + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, > + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, > + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, > + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, > + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, > + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, > + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, > + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, > + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, > + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, > + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, > + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, > +}; > + > +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { > + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, > + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, > + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, > + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, > + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, > + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, > + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, > + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, > + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, > + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, > + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, > + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, > + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, > + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, > + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, > + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, > +}; > + > +static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = { > + [DBSC3_00] = DBSC3_1_QOS_R0_BASE, > + [DBSC3_01] = DBSC3_1_QOS_R1_BASE, > + [DBSC3_02] = DBSC3_1_QOS_R2_BASE, > + [DBSC3_03] = DBSC3_1_QOS_R3_BASE, > + [DBSC3_04] = DBSC3_1_QOS_R4_BASE, > + [DBSC3_05] = DBSC3_1_QOS_R5_BASE, > + [DBSC3_06] = DBSC3_1_QOS_R6_BASE, > + [DBSC3_07] = DBSC3_1_QOS_R7_BASE, > + [DBSC3_08] = DBSC3_1_QOS_R8_BASE, > + [DBSC3_09] = DBSC3_1_QOS_R9_BASE, > + [DBSC3_10] = DBSC3_1_QOS_R10_BASE, > + [DBSC3_11] = DBSC3_1_QOS_R11_BASE, > + [DBSC3_12] = DBSC3_1_QOS_R12_BASE, > + [DBSC3_13] = DBSC3_1_QOS_R13_BASE, > + [DBSC3_14] = DBSC3_1_QOS_R14_BASE, > + [DBSC3_15] = DBSC3_1_QOS_R15_BASE, > +}; > + > +static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = { > + [DBSC3_00] = DBSC3_1_QOS_W0_BASE, > + [DBSC3_01] = DBSC3_1_QOS_W1_BASE, > + [DBSC3_02] = DBSC3_1_QOS_W2_BASE, > + [DBSC3_03] = DBSC3_1_QOS_W3_BASE, > + [DBSC3_04] = DBSC3_1_QOS_W4_BASE, > + [DBSC3_05] = DBSC3_1_QOS_W5_BASE, > + [DBSC3_06] = DBSC3_1_QOS_W6_BASE, > + [DBSC3_07] = DBSC3_1_QOS_W7_BASE, > + [DBSC3_08] = DBSC3_1_QOS_W8_BASE, > + [DBSC3_09] = DBSC3_1_QOS_W9_BASE, > + [DBSC3_10] = DBSC3_1_QOS_W10_BASE, > + [DBSC3_11] = DBSC3_1_QOS_W11_BASE, > + [DBSC3_12] = DBSC3_1_QOS_W12_BASE, > + [DBSC3_13] = DBSC3_1_QOS_W13_BASE, > + [DBSC3_14] = DBSC3_1_QOS_W14_BASE, > + [DBSC3_15] = DBSC3_1_QOS_W15_BASE, > +}; > + > +void qos_init(void) > +{ > + int i; > + struct rcar_s3c *s3c; > + struct rcar_s3c_qos *s3c_qos; > + struct rcar_dbsc3_qos *qos_addr; > + struct rcar_mxi *mxi; > + struct rcar_mxi_qos *mxi_qos; > + struct rcar_axi_qos *axi_qos; > + > + /* DBSC DBADJ2 */ > + writel(0x20042004, DBSC3_0_DBADJ2); > + writel(0x20042004, DBSC3_1_DBADJ2); > + > + /* S3C -QoS */ > + s3c = (struct rcar_s3c *)S3C_BASE; > + if (IS_R8A7791_ES2()) { > + /* Linear All mode */ > + /* writel(0x00000000, &s3c->s3cadsplcr); */ > + /* Linear Linear 0x7000 to 0x7800 mode */ > + writel(0x00BF1B0C, &s3c->s3cadsplcr); > + /* Split Linear 0x6800 t 0x7000 mode */ > + /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ > + /* Ssplit All mode */ > + /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */ > + writel(0x1F0B0908, &s3c->s3crorr); > + writel(0x1F0C0A08, &s3c->s3cworr); > + } else { > + writel(0x00FF1B1D, &s3c->s3cadsplcr); > + writel(0x1F0D0C0C, &s3c->s3crorr); > + writel(0x1F0D0C0A, &s3c->s3cworr); > + } > + /* QoS Control Registers */ > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; > + writel(0x00890089, &s3c_qos->s3cqos0); > + writel(0x20960010, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA2200, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960010, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA2200, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; > + writel(0x00890089, &s3c_qos->s3cqos0); > + writel(0x20960010, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA2200, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960010, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA2200, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; > + writel(0x00820082, &s3c_qos->s3cqos0); > + writel(0x20960020, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA20DC, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960020, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA20DC, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; > + writel(0x00820082, &s3c_qos->s3cqos0); > + writel(0x20960020, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA20FA, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960020, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA20FA, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + /* DBSC -QoS */ > + /* DBSC0 - Read */ > + for (i = DBSC3_00; i < DBSC3_NR; i++) { > + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; > + writel(0x00000002, &qos_addr->dblgcnt); > + writel(0x00002096, &qos_addr->dbtmval0); > + writel(0x00002064, &qos_addr->dbtmval1); > + writel(0x00002032, &qos_addr->dbtmval2); > + writel(0x00001FB0, &qos_addr->dbtmval3); > + writel(0x00000001, &qos_addr->dbrqctr); > + writel(0x00002078, &qos_addr->dbthres0); > + writel(0x0000204B, &qos_addr->dbthres1); > + writel(0x0000201E, &qos_addr->dbthres2); > + writel(0x00000001, &qos_addr->dblgqon); > + } > + > + /* DBSC0 - Write */ > + for (i = DBSC3_00; i < DBSC3_NR; i++) { > + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; > + writel(0x00000002, &qos_addr->dblgcnt); > + writel(0x00002096, &qos_addr->dbtmval0); > + writel(0x00002064, &qos_addr->dbtmval1); > + writel(0x00002050, &qos_addr->dbtmval2); > + writel(0x0000203A, &qos_addr->dbtmval3); > + writel(0x00000001, &qos_addr->dbrqctr); > + writel(0x00002078, &qos_addr->dbthres0); > + writel(0x0000204B, &qos_addr->dbthres1); > + writel(0x0000203C, &qos_addr->dbthres2); > + writel(0x00000001, &qos_addr->dblgqon); > + } > + > + /* DBSC1 - Read */ > + for (i = DBSC3_00; i < DBSC3_NR; i++) { > + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i]; > + writel(0x00000002, &qos_addr->dblgcnt); > + writel(0x00002096, &qos_addr->dbtmval0); > + writel(0x00002064, &qos_addr->dbtmval1); > + writel(0x00002032, &qos_addr->dbtmval2); > + writel(0x00001FB0, &qos_addr->dbtmval3); > + writel(0x00000001, &qos_addr->dbrqctr); > + writel(0x00002078, &qos_addr->dbthres0); > + writel(0x0000204B, &qos_addr->dbthres1); > + writel(0x0000201E, &qos_addr->dbthres2); > + writel(0x00000001, &qos_addr->dblgqon); > + } > + > + /* DBSC1 - Write */ > + for (i = DBSC3_00; i < DBSC3_NR; i++) { > + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i]; > + writel(0x00000002, &qos_addr->dblgcnt); > + writel(0x00002096, &qos_addr->dbtmval0); > + writel(0x00002064, &qos_addr->dbtmval1); > + writel(0x00002050, &qos_addr->dbtmval2); > + writel(0x0000203A, &qos_addr->dbtmval3); > + writel(0x00000001, &qos_addr->dbrqctr); > + writel(0x00002078, &qos_addr->dbthres0); > + writel(0x0000204B, &qos_addr->dbthres1); > + writel(0x0000203C, &qos_addr->dbthres2); > + writel(0x00000001, &qos_addr->dblgqon); > + } > + > + /* CCI-400 -QoS */ > + writel(0x20001000, CCI_400_MAXOT_1); > + writel(0x20001000, CCI_400_MAXOT_2); > + writel(0x0000000C, CCI_400_QOSCNTL_1); > + writel(0x0000000C, CCI_400_QOSCNTL_2); > + > + /* MXI -QoS */ > + /* Transaction Control (MXI) */ > + mxi = (struct rcar_mxi *)MXI_BASE; > + writel(0x00000013, &mxi->mxrtcr); > + writel(0x00000013, &mxi->mxwtcr); > + > + /* QoS Control (MXI) */ > + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; > + writel(0x0000000C, &mxi_qos->vspdu0); > + writel(0x0000000C, &mxi_qos->vspdu1); > + writel(0x0000000E, &mxi_qos->du0); > + writel(0x0000000D, &mxi_qos->du1); > + > + /* AXI -QoS */ > + /* Transaction Control (MXI) */ > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002021, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002037, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002021, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002021, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002029, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (RT-AXI) */ > + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002299, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002029, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002029, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (MP-AXI) */ > + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002037, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002014, &axi_qos->qosctset0); > + writel(0x00000040, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002014, &axi_qos->qosctset0); > + writel(0x00000040, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00001FF0, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00002001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000206E, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (SYS-AXI256) */ > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + if (IS_R8A7791_ES2()) > + writel(0x000020EB, &axi_qos->qosctset0); > + else > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + if (IS_R8A7791_ES2()) > + writel(0x000020EB, &axi_qos->qosctset0); > + else > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + if (IS_R8A7791_ES2()) > + writel(0x000020EB, &axi_qos->qosctset0); > + else > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (CCI-AXI) */ > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (Media-AXI) */ > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020DC, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x000020AA, &axi_qos->qosthres0); > + writel(0x00002032, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020DC, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x000020AA, &axi_qos->qosthres0); > + writel(0x00002032, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + if (IS_R8A7791_ES2()) > + writel(0x00001FF0, &axi_qos->qosctset0); > + else > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + if (IS_R8A7791_ES2()) > + writel(0x00002001, &axi_qos->qosthres2); > + else > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; > + if (IS_R8A7791_ES2()) > + writel(0x00000003, &axi_qos->qosconf); > + else > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; > + if (IS_R8A7791_ES2()) > + writel(0x00000003, &axi_qos->qosconf); > + else > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; > + if (IS_R8A7791_ES2()) > + writel(0x00000003, &axi_qos->qosconf); > + else > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; > + if (IS_R8A7791_ES2()) > + writel(0x00000003, &axi_qos->qosconf); > + else > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; > + if (IS_R8A7791_ES2()) > + writel(0x00000003, &axi_qos->qosconf); > + else > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002063, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; > + if (IS_R8A7791_ES2()) > + writel(0x00000000, &axi_qos->qosconf); > + else > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002063, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + if (IS_R8A7791_ES2()) { > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + } else { > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + } > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > +} > +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ > +void qos_init(void) > +{ > +} > +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ > diff --git a/board/renesas/porter/qos.h b/board/renesas/porter/qos.h > new file mode 100644 > index 0000000..75a20bb > --- /dev/null > +++ b/board/renesas/porter/qos.h > @@ -0,0 +1,13 @@ > +/* > + * Copyright (C) 2015 Renesas Electronics Corporation > + * Copyright (C) 2015 Cogent Embedded, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#ifndef __QOS_H__ > +#define __QOS_H__ > + > +void qos_init(void); > + > +#endif > diff --git a/configs/porter_defconfig b/configs/porter_defconfig > new file mode 100644 > index 0000000..8d594d9 > --- /dev/null > +++ b/configs/porter_defconfig > @@ -0,0 +1,6 @@ > +CONFIG_ARM=y > +CONFIG_RMOBILE=y > +CONFIG_TARGET_PORTER=y > +CONFIG_DM=y > +CONFIG_DM_SERIAL=y > +CONFIG_SH_SDHI=y > diff --git a/include/configs/porter.h b/include/configs/porter.h > new file mode 100644 > index 0000000..9703c84 > --- /dev/null > +++ b/include/configs/porter.h > @@ -0,0 +1,112 @@ > +/* > + * include/configs/porter.h > + * This file is Porter board configuration. > + * > + * Copyright (C) 2015 Renesas Electronics Corporation > + * Copyright (C) 2015 Cogent Embedded, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#ifndef __PORTER_H > +#define __PORTER_H > + > +#undef DEBUG > +#define CONFIG_R8A7791 > +#define CONFIG_RMOBILE_BOARD_STRING "Porter" > + > +#include "rcar-gen2-common.h" > + > +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) > +#define CONFIG_SYS_TEXT_BASE 0x70000000 > +#else > +#define CONFIG_SYS_TEXT_BASE 0xE6304000 > +#endif > + > +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) > +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC > +#else > +#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC > +#endif > +#define STACK_AREA_SIZE 0xC000 > +#define LOW_LEVEL_MERAM_STACK \ > + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) > + > +/* MEMORY */ > +#define RCAR_GEN2_SDRAM_BASE 0x40000000 > +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) > +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) > + > +/* SCIF */ > +#define CONFIG_SCIF_CONSOLE > + > +/* FLASH */ > +#define CONFIG_SPI > +#define CONFIG_SPI_FLASH_BAR > +#define CONFIG_SH_QSPI > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_SPANSION > +#define CONFIG_SPI_FLASH_QUAD > +#define CONFIG_SYS_NO_FLASH > + > +/* SH Ether */ > +#define CONFIG_NET_MULTI > +#define CONFIG_SH_ETHER > +#define CONFIG_SH_ETHER_USE_PORT 0 > +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 > +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII > +#define CONFIG_SH_ETHER_CACHE_WRITEBACK > +#define CONFIG_SH_ETHER_CACHE_INVALIDATE > +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 > +#define CONFIG_PHYLIB > +#define CONFIG_PHY_MICREL > +#define CONFIG_BITBANGMII > +#define CONFIG_BITBANGMII_MULTI > + > +/* Board Clock */ > +#define RMOBILE_XTAL_CLK 20000000u > +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK > +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) > +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) > +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) > + > +#define CONFIG_SYS_TMU_CLK_DIV 4 > + > +/* i2c */ > +#define CONFIG_CMD_I2C > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_SH > +#define CONFIG_SYS_I2C_SLAVE 0x7F > +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 > +#define CONFIG_SYS_I2C_SH_SPEED0 400000 > +#define CONFIG_SYS_I2C_SH_SPEED1 400000 > +#define CONFIG_SYS_I2C_SH_SPEED2 400000 > +#define CONFIG_SH_I2C_DATA_HIGH 4 > +#define CONFIG_SH_I2C_DATA_LOW 5 > +#define CONFIG_SH_I2C_CLOCK 10000000 > + > +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ > + > +/* USB */ > +#define CONFIG_USB_EHCI > +#define CONFIG_USB_EHCI_RMOBILE > +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 > +#define CONFIG_USB_STORAGE > + > +/* SD */ > +#define CONFIG_MMC > +#define CONFIG_CMD_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_SH_SDHI_FREQ 97500000 > + > +/* Module stop status bits */ > +/* INTC-RT */ > +#define CONFIG_SMSTP0_ENA 0x00400000 > +/* MSIF */ > +#define CONFIG_SMSTP2_ENA 0x00002000 > +/* INTC-SYS, IRQC */ > +#define CONFIG_SMSTP4_ENA 0x00000180 > +/* SCIF0 */ > +#define CONFIG_SMSTP7_ENA 0x00200000 > + > +#endif /* __PORTER_H */ > -- > 1.9.1 > > _______________________________________________ > U-Boot mailing list > [email protected] > http://lists.denx.de/mailman/listinfo/u-boot -- Nobuhiro Iwamatsu _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
