From: Praveen Rao <p...@ti.com>
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.
Signed-off-by: Praveen Rao <p...@ti.com>
Signed-off-by: Angela Stegmaier <angelaba...@ti.com>
Signed-off-by: Nishanth Menon <n...@ti.com>
---
arch/arm/cpu/armv7/omap5/hwinit.c | 7 +++++++
arch/arm/include/asm/arch-omap5/sys_proto.h | 4 ++++
include/configs/ti_omap5_common.h | 3 +++
3 files changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index a8a474a88be9..f8060555b680 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -381,3 +381,10 @@ void setup_warmreset_time(void)
rst_val |= rst_time;
writel(rst_val, (*prcm)->prm_rsttime);
}
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
+}
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 103830319a41..37dc9925eae2 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -66,4 +66,8 @@ static inline u32 usec_to_32k(u32 usec)
{
return div_round_up(32768 * usec, 1000000);
}
+
+void omap_smc1(u32 service, u32 val);
+#define OMAP5_SERVICE_L2ACTLR_SET 0x104
+
#endif
diff --git a/include/configs/ti_omap5_common.h
b/include/configs/ti_omap5_common.h
index 925cb42dd38d..09f05f18a75d 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -21,6 +21,9 @@
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ARCH_CPU_INIT
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_798870
+
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Use General purpose timer 1 */
--
1.7.9.5
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
