On Friday, March 13, 2015 at 05:35:53 PM, Stephen Warren wrote: > On 03/13/2015 08:30 AM, Marek Vasut wrote: > > On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote: > >> BCM2835 bus addresses use the top 2 bits to determine whether > >> peripherals use or bypass the GPU L1 and L2 cache. > >> BCM2835-ARM-Peripherals.pdf states that: > >> > >> 0: L1 & L2 cached > >> 4: L2 cache coherent (non allocaing) > >> 8: L2 cached only > >> c: Direct uncached. > > > > Caches aren't working on BCM2xxx or what's the reason for this hack ? > > Or are these different (not on-CPU) caches we're talking about (yes, > > I did notice the GPU Lx cache stuff)? > > Yes, the "GPU" has its own caches, entirely separate from the ARM core > and at a different location in the system bus structure, and it seems as > if at least some other peripherals other than GPU/graphics/VideoCore > access DRAM via those caches too. > > There are some brief details in BCM2835-ARM-Peripherals.pdf, although it > isn't terribly clear.
Thanks for clearing this up. I suspect there's no way to turn those caches off altogether, right ? But uh ... ew :( Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
