On Thu, Mar 19, 2015 at 04:45:35PM +0000, York Sun wrote:
> The timer clock is system clock divided by 4, not fixed 12MHz. This is
> common to the SoC, not board specific.
>
> Signed-off-by: York Sun <york...@freescale.com>
> ---
> README | 8 ++++++++
> arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24 ++++++++++++++++++++++++
> board/freescale/ls2085a/ls2085a.c | 18 ------------------
> include/configs/ls2085a_common.h | 6 +++++-
> 4 files changed, 37 insertions(+), 19 deletions(-)
>
> diff --git a/README b/README
> index f473515..776ebf4 100644
> --- a/README
> +++ b/README
> @@ -690,6 +690,14 @@ The following options need to be configured:
> exists, unlike the similar options in the Linux kernel. Do not
> set these options unless they apply!
>
> + COUNTER_FREQUENCY
> + Generic timer clock source frequency.
> +
> + COUNTER_FREQUENCY_REAL
> + Generic timer clock source frequency if the real clock is
> + different from COUNTER_FREQUENCY, and can only be determined
> + at run time.
> +
> NOTE: The following can be machine specific errata. These
> do have ability to provide rudimentary version and machine
> specific checks, but expect no product checks.
> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
> b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
> index 94fd147..e985181 100644
> --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
> @@ -395,3 +395,27 @@ int arch_early_init_r(void)
>
> return 0;
> }
> +
> +int timer_init(void)
> +{
> + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
> + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
> +#ifdef COUNTER_FREQUENCY_REAL
> + unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
> +
> + /* Update with accurate clock frequency */
> + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
> +#endif
Is this executed on all CPUs, or do secondary CPUs have CNTFRQ
programmed with the correct value elsewhere?
Mark.
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