On 03/19/2015 09:30 AM, York Sun wrote: > Add/update registers for DDR4, including DQ mappings. Allow raw timing > method used for all controllers. Update mode_9 register to 0x500 for > improved stability. Check DDR controller version number individually > in case a SoC has multiple DDR controllers of different versions. > Increase read-write turnaround for DDR4 high speeds. > > Signed-off-by: York Sun <[email protected]> > ---
This set is applied to fsl-qoriq master, awaiting upstream. [U-Boot,1/4] drivers/ddr/fsl: Update DDR driver for DDR4 [U-Boot,2/4] driver/ddr/fsl: Fix driver to support empty first slot [U-Boot,3/4] driver/ddr/fsl: Add built-in memory test for DDR4 driver [U-Boot,4/4] driver/ddr/fsl: Add workaround for DDR erratum A008511 York _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
