Hi Simon,
On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass <s...@chromium.org> wrote:
> This driver supports multi-core init and sets up the CPU frequencies
> correctly.
>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
>
> Changes in v2: None
>
> arch/x86/cpu/baytrail/Makefile | 1 +
> arch/x86/cpu/baytrail/cpu.c | 206
> +++++++++++++++++++++++++++++++
> arch/x86/include/asm/arch-baytrail/msr.h | 30 +++++
> 3 files changed, 237 insertions(+)
> create mode 100644 arch/x86/cpu/baytrail/cpu.c
> create mode 100644 arch/x86/include/asm/arch-baytrail/msr.h
>
> diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
> index 8914e8b..c78b644 100644
> --- a/arch/x86/cpu/baytrail/Makefile
> +++ b/arch/x86/cpu/baytrail/Makefile
> @@ -4,6 +4,7 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> +obj-y += cpu.o
> obj-y += early_uart.o
> obj-y += fsp_configs.o
> obj-y += pci.o
> diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
> new file mode 100644
> index 0000000..5a2a8ee
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/cpu.c
> @@ -0,0 +1,206 @@
> +/*
> + * Copyright (C) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Based on code from coreboot
> + */
> +
> +#include <common.h>
> +#include <cpu.h>
> +#include <dm.h>
> +#include <asm/cpu.h>
> +#include <asm/lapic.h>
> +#include <asm/mp.h>
> +#include <asm/msr.h>
> +#include <asm/turbo.h>
> +#include <asm/arch/msr.h>
> +
> +#ifdef CONFIG_SMP
> +static int enable_smis(struct udevice *cpu, void *unused)
> +{
> + return 0;
> +}
> +
> +static struct mp_flight_record mp_steps[] = {
> + MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
> + /* Wait for APs to finish initialization before proceeding. */
> + MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
> +};
> +
> +static int detect_num_cpus(void)
> +{
> + int ecx = 0;
> +
> + /*
> + * Use the algorithm described in Intel 64 and IA-32 Architectures
> + * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
> + * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
> + * of CPUID Extended Topology Leaf.
> + */
> + while (1) {
> + struct cpuid_result leaf_b;
> +
> + leaf_b = cpuid_ext(0xb, ecx);
> +
> + /*
> + * Bay Trail doesn't have hyperthreading so just determine the
> + * number of cores by from level type (ecx[15:8] == * 2)
> + */
> + if ((leaf_b.ecx & 0xff00) == 0x0200)
> + return leaf_b.ebx & 0xffff;
> + ecx++;
> + }
> +}
> +
> +static int baytrail_init_cpus(void)
> +{
> + struct mp_params mp_params;
> +
> + lapic_setup();
One more comment, I believe this lapic_setup() call can be moved into
mp_init(), thoughts?
> +
> + mp_params.num_cpus = detect_num_cpus();
> + mp_params.parallel_microcode_load = 0,
> + mp_params.flight_plan = &mp_steps[0];
> + mp_params.num_records = ARRAY_SIZE(mp_steps);
> + mp_params.microcode_pointer = 0;
> +
> + if (mp_init(&mp_params)) {
> + printf("Warning: MP init failure\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +#endif
[snip]
Regards,
Bin
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