> + > +#include <config.h> > + > +#ifdef CONFIG_S3C24X0 > + > +/* Register addresses. */ > +# ifdef CONFIG_S3C2400 > + #define pWTCON 0x15300000 > + #define INTMSK 0x14400008 > + #define CLKDIVN 0x14800014 > +#else > + #define pWTCON 0x53000000 > + #define INTMSK 0x4A000008 > + #define INTSUBMSK 0x4A00001C > + #define CLKDIVN 0x4C000014 > +#endif pplease move this to soc header > + > +/* Configuration values. */ > +#ifdef CONFIG_S3C2440 > + #define INTSMASK 0xffff > + #define CLKDIVVAL 0x5 > +#else > + #define INTSMASK 0x3ff > + #define CLKDIVVAL 0x3 > +#endif ditto > + > +.globl arch_pre_lowlevel_init > +arch_pre_lowlevel_init: > + > + /* turn off the watchdog */ > + ldr r0, =pWTCON > + mov r1, #0x0 > + str r1, [r0] > + > + /* > + * mask all IRQs by setting all bits in the INTMR - default > + */ > + mov r1, #0xffffffff > + ldr r0, =INTMSK > + str r1, [r0] > +# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) > + ldr r1, =INTSMASK > + ldr r0, =INTSUBMSK > + str r1, [r0] > +# endif > + > + /* FCLK:HCLK:PCLK = 1:2:4 */ > + /* default FCLK is 120 MHz ! */ > + ldr r0, =CLKDIVN > + mov r1, #CLKDIVVAL > + str r1, [r0] > + > +#ifdef CONFIG_S3C2440 > + /* Set asynchronous bus mode */ > + mrc p15, 0, r1, c1, c0, 0 /* read ctrl register */ whitespace please fix > + orr r1, r1, #0xc0000000 /* Asynchronous */ whitespace please fix > + mcr p15, 0, r1, c1, c0, 0 /* write ctrl register */ whitespace please fix > +#endif /* CONFIG_S3C2440 */ whitespace please fix > + > + mov pc, lr > + > +#endif /* CONFIG_S3C24X0 */ whitespace please fix > diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c > index bb86335..95c4407 100644 > --- a/cpu/arm920t/s3c24x0/speed.c > +++ b/cpu/arm920t/s3c24x0/speed.c > @@ -30,15 +30,10 @@ > */ > > #include <common.h> > -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined > (CONFIG_TRAB) > +#ifdef CONFIG_S3C24X0 > > #include <asm/io.h> > - > -#if defined(CONFIG_S3C2400) > -#include <s3c2400.h> > -#elif defined(CONFIG_S3C2410) > -#include <s3c2410.h> > -#endif > +#include <s3c24x0_cpu.h> > > #define MPLL 0 > #define UPLL 1 > @@ -69,6 +64,11 @@ static ulong get_PLLCLK(int pllreg) please rename it as get_pll_clk_rate > p = ((r & 0x003F0) >> 4) + 2; > s = r & 0x3; > > +#ifdef CONFIG_S3C2440 > + if (pllreg == MPLL) > + return (2 * CONFIG_SYS_CLK_FREQ * m) / (p << s); > + else > +#endif > return (CONFIG_SYS_CLK_FREQ * m) / (p << s); > } > > @@ -83,7 +83,23 @@ ulong get_HCLK(void) please use this style get_xxx_clk_rate
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