Signed-off-by: Vikas Manocha <[email protected]>
---
drivers/spi/cadence_qspi_apb.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 403230a..e1e1315 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -471,6 +471,10 @@ void cadence_qspi_apb_controller_init(struct
cadence_spi_platdata *plat)
/* Configure the remap address register, no remap */
writel(0, plat->regbase + CQSPI_REG_REMAP);
+ /* Setup the indirect trigger address */
+ writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
+ plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
+
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
@@ -629,10 +633,6 @@ int cadence_qspi_apb_indirect_read_setup(struct
cadence_spi_platdata *plat,
/* for normal read (only ramtron as of now) */
addr_bytes = cmdlen - 1;
- /* Setup the indirect trigger address */
- writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
- plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
-
/* Configure SRAM partition for read. */
writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
CQSPI_REG_SRAMPARTITION);
@@ -731,9 +731,6 @@ int cadence_qspi_apb_indirect_write_setup(struct
cadence_spi_platdata *plat,
cmdlen, (unsigned int)cmdbuf);
return -EINVAL;
}
- /* Setup the indirect trigger address */
- writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
- plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
writel(CQSPI_REG_SRAM_PARTITION_WR,
plat->regbase + CQSPI_REG_SRAMPARTITION);
--
1.7.9.5
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