On 24 June 2015 at 23:43, Vikas MANOCHA <[email protected]> wrote: > Thanks Stefan, > Adding Jagan to apply the patchset.
I saw checkpatch.pl errors/warnings with 1 and 3 patches, please check it those and resend. Anyway I will apply these on master-next for next releases, is that fine? > >> -----Original Message----- >> From: Stefan Roese [mailto:[email protected]] >> Sent: Wednesday, June 24, 2015 3:09 AM >> To: Vikas MANOCHA >> Cc: [email protected]; [email protected]; >> [email protected] >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for >> FIFO width >> >> Hi Vikas, >> >> On 23.06.2015 16:48, Vikas MANOCHA wrote: >> >> -----Original Message----- >> >> From: Stefan Roese [mailto:[email protected]] >> >> Sent: Friday, June 12, 2015 5:10 AM >> >> To: Vikas MANOCHA; [email protected]; >> >> [email protected]; [email protected] >> >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix >> >> for FIFO width >> >> >> >> Hi Vikas, >> >> >> >> On 11.06.2015 21:16, Vikas MANOCHA wrote: >> >>> Any comments on the patchset. >> >> >> >> I'll test them next week on a SoCFPGA based board and will comment >> >> then again. >> > >> > Can you please test this patchset also. >> >> Okay. I've now tested this 3 patch series as well on top of mainline. >> And SPI NOR seems to work just fine with this one applied. Not errors and >> the write/read/compare test also works okay. thanks! -- Jagan | openedev. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
