On Mon, Jun 29, 2015 at 11:58 AM, Peng Fan <[email protected]> wrote: > 1. Add DDR script for mx6qpsabreauto board. > 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] > and init the enet pll output to 125Mhz. > 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. > > Build target: mx6qpsabreauto_config > > Boot Log: > U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800) > > CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) > CPU: Automotive temperature grade (-40C to 125C) at 34C > Reset cause: POR > Board: MX6Q-Sabreauto revA > I2C: ready > DRAM: 2 GiB > PMIC: PFUZE100 ID=0x10 > Flash: 32 MiB > NAND: 0 MiB > MMC: FSL_SDHC: 0 > *** Warning - bad CRC, using default environment > > No panel detected: default to HDMI > Display: HDMI (1024x768) > In: serial > Out: serial > Err: serial > Net: FEC [PRIME] > Hit any key to stop autoboot: 0 > > Note: > In this patch, we still add a new config mx6qpsabreauto_config, > since SPL is not supported now, and IMX_CONFIG is needed at > build time, so add this config. Future, when SPL is converted, > this config can be removed. > > Signed-off-by: Robin Gong <[email protected]> > Signed-off-by: Ye.Li <[email protected]> > Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
