Scott, I lost track on your progress. Please let me know if I should hold this one or drop it.
York On 04/22/2015 07:26 PM, Scott Wood wrote: > On Wed, 2015-04-22 at 18:13 +0200, Alexander Graf wrote: >> The QEMU u-boot located itself at a 4k aligned offset which the rest >> of the code didn't really expect. Align it with 64k to allow the memory >> code to deal with 64k granularity. >> >> This fixes broken interrupt delivery with the ppce500 machine for me. >> >> Signed-off-by: Alexander Graf <[email protected]> >> --- >> include/configs/qemu-ppce500.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h >> index 7071849..ec90797 100644 >> --- a/include/configs/qemu-ppce500.h >> +++ b/include/configs/qemu-ppce500.h >> @@ -18,7 +18,7 @@ >> #define CONFIG_QEMU_E500 >> >> #undef CONFIG_SYS_TEXT_BASE >> -#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ >> +#define CONFIG_SYS_TEXT_BASE 0xf10000 /* 15 MB */ >> #define CONFIG_SYS_GENERIC_BOARD >> >> #define CONFIG_SYS_MPC85XX_NO_RESETVEC > > I think we have a similar problem with NAND, SD, etc. boot on some > targets. I'll try to fix it so that the existing addresses work. > > -Scott > > _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
