On 30 June 2015 at 02:19, Vikas Manocha <[email protected]> wrote: > sram size could be different on different socs, e.g. on stv0991 it is 256 > while > on altera platform it is 128. It is better to receive it from device tree. > > Signed-off-by: Vikas Manocha <[email protected]>
Still have an issue - unable to apply. > Tested-by: Stefan Roese <[email protected]> > --- > > Changes in v3: Rebased to spi-next-dev > Changes in v2: None > > arch/arm/dts/socfpga.dtsi | 1 + > arch/arm/dts/stv0991.dts | 1 + > drivers/spi/cadence_qspi.c | 1 + > drivers/spi/cadence_qspi.h | 1 + > drivers/spi/cadence_qspi_apb.c | 6 +----- > 5 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi > index bf791c5..9b12420 100644 > --- a/arch/arm/dts/socfpga.dtsi > +++ b/arch/arm/dts/socfpga.dtsi > @@ -639,6 +639,7 @@ > ext-decoder = <0>; /* external decoder */ > num-cs = <4>; > fifo-depth = <128>; > + sram-size = <128>; > bus-num = <2>; > status = "disabled"; > }; > diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts > index 3b1efca..556df82 100644 > --- a/arch/arm/dts/stv0991.dts > +++ b/arch/arm/dts/stv0991.dts > @@ -35,6 +35,7 @@ > ext-decoder = <0>; /* external decoder */ > num-cs = <4>; > fifo-depth = <256>; > + sram-size = <256>; > bus-num = <0>; > status = "okay"; > > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > index a75fc46..34a0f46 100644 > --- a/drivers/spi/cadence_qspi.c > +++ b/drivers/spi/cadence_qspi.c > @@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice > *bus) > plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); > plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); > plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); > + plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); > > debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", > __func__, plat->regbase, plat->ahbbase, plat->max_hz, > diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h > index c9a6142..98e57aa 100644 > --- a/drivers/spi/cadence_qspi.h > +++ b/drivers/spi/cadence_qspi.h > @@ -25,6 +25,7 @@ struct cadence_spi_platdata { > u32 tsd2d_ns; > u32 tchsh_ns; > u32 tslch_ns; > + u32 sram_size; > }; > > struct cadence_spi_priv { > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c > index f2c22af..cbf0d42 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -36,9 +36,6 @@ > > #define CQSPI_FIFO_WIDTH (4) > > -/* Controller sram size in word */ > -#define CQSPI_REG_SRAM_SIZE_WORD (128) > -#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2) > #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) > > /* Transfer mode */ > @@ -536,8 +533,7 @@ void cadence_qspi_apb_controller_init(struct > cadence_spi_platdata *plat) > writel(0, plat->regbase + CQSPI_REG_REMAP); > > /* Indirect mode configurations */ > - writel(CQSPI_REG_SRAM_PARTITION_RD, > - plat->regbase + CQSPI_REG_SRAMPARTITION); > + writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); > > /* Disable all interrupts */ > writel(0, plat->regbase + CQSPI_REG_IRQMASK); > -- > 1.7.9.5 thanks! -- Jagan | openedev. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
