This is effectively the same code but it also does a clean cache before invalidating and doing a memory barrier.
Signed-off-by: Alexander Stein <[email protected]> --- arch/arm/cpu/arm1176/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c index 2d81651..24b5cc7 100644 --- a/arch/arm/cpu/arm1176/cpu.c +++ b/arch/arm/cpu/arm1176/cpu.c @@ -41,11 +41,13 @@ int cleanup_before_linux (void) return 0; } -/* flush I/D-cache */ -static void cache_flush (void) +static void cache_flush(void) { + unsigned long i = 0; + /* clean entire data cache */ + asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0)); + asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i)); /* mem barrier to sync things */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); } -- 2.4.5 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
