Hi Bin, On 6 July 2015 at 02:31, Bin Meng <[email protected]> wrote: > We should setup fixed range MTRRs for some legacy regions like VGA > RAM and PCI ROM areas as uncacheable. Note FSP may setup these to > other cache settings, but we can override this in x86_cpu_init_f(). > > Signed-off-by: Bin Meng <[email protected]> > Acked-by: Simon Glass <[email protected]> > --- > > Changes in v2: None > > arch/x86/cpu/cpu.c | 22 ++++++++++++++++++++++ > arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++----------- > 2 files changed, 38 insertions(+), 11 deletions(-) > > diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c > index d108ee5..9afdafb 100644 > --- a/arch/x86/cpu/cpu.c > +++ b/arch/x86/cpu/cpu.c > @@ -28,6 +28,8 @@ > #include <asm/cpu.h> > #include <asm/lapic.h> > #include <asm/mp.h> > +#include <asm/msr.h> > +#include <asm/mtrr.h> > #include <asm/post.h> > #include <asm/processor.h> > #include <asm/processor-flags.h> > @@ -352,6 +354,26 @@ int x86_cpu_init_f(void) > gd->arch.has_mtrr = has_mtrr(); > } > > + /* Configure fixed range MTRRs for some legacy regions */ > + if (gd->arch.has_mtrr) { > + u64 mtrr_cap; > + > + mtrr_cap = native_read_msr(MTRR_CAP_MSR); > + if (mtrr_cap & MTRR_CAP_FIX) { > + /* Mark the VGA RAM area as uncacheable */ > + native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0); > + > + /* Mark the PCI ROM area as uncacheable */ > + native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0); > + native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0); > + native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0); > + native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
I just noticed that setting this up makes the Minnowmax ROM execution go really slowly. Do we need to turn off the cache? It goes from <1s to >4s. > + > + /* Enable the fixed range MTRRs */ > + msr_setbits_64(MTRR_DEF_TYPE_MSR, > MTRR_DEF_TYPE_FIX_EN); > + } > + } > + > return 0; > } > > diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h > index 3ad617c..70762ee 100644 > --- a/arch/x86/include/asm/mtrr.h > +++ b/arch/x86/include/asm/mtrr.h > @@ -21,6 +21,11 @@ > #define MTRR_CAP_MSR 0x0fe > #define MTRR_DEF_TYPE_MSR 0x2ff > > +#define MTRR_CAP_SMRR (1 << 11) > +#define MTRR_CAP_WC (1 << 10) > +#define MTRR_CAP_FIX (1 << 8) > +#define MTRR_CAP_VCNT_MASK 0xff > + > #define MTRR_DEF_TYPE_EN (1 << 11) > #define MTRR_DEF_TYPE_FIX_EN (1 << 10) > > @@ -38,17 +43,17 @@ > #define RANGES_PER_FIXED_MTRR 8 > #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) > > -#define MTRR_FIX_64K_00000_MSR 0x250 > -#define MTRR_FIX_16K_80000_MSR 0x258 > -#define MTRR_FIX_16K_A0000_MSR 0x259 > -#define MTRR_FIX_4K_C0000_MSR 0x268 > -#define MTRR_FIX_4K_C8000_MSR 0x269 > -#define MTRR_FIX_4K_D0000_MSR 0x26a > -#define MTRR_FIX_4K_D8000_MSR 0x26b > -#define MTRR_FIX_4K_E0000_MSR 0x26c > -#define MTRR_FIX_4K_E8000_MSR 0x26d > -#define MTRR_FIX_4K_F0000_MSR 0x26e > -#define MTRR_FIX_4K_F8000_MSR 0x26f > +#define MTRR_FIX_64K_00000_MSR 0x250 > +#define MTRR_FIX_16K_80000_MSR 0x258 > +#define MTRR_FIX_16K_A0000_MSR 0x259 > +#define MTRR_FIX_4K_C0000_MSR 0x268 > +#define MTRR_FIX_4K_C8000_MSR 0x269 > +#define MTRR_FIX_4K_D0000_MSR 0x26a > +#define MTRR_FIX_4K_D8000_MSR 0x26b > +#define MTRR_FIX_4K_E0000_MSR 0x26c > +#define MTRR_FIX_4K_E8000_MSR 0x26d > +#define MTRR_FIX_4K_F0000_MSR 0x26e > +#define MTRR_FIX_4K_F8000_MSR 0x26f > > #if !defined(__ASSEMBLER__) > > -- > 1.8.2.1 > Regards, Simon _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
