ps-clk-frequency is platform specific setting and shouldn't be the part
of DTSI.
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---
Sync with mainline.
---
arch/arm/dts/zynq-7000.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a1de993b9812..095c0f67e167 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -241,7 +241,6 @@
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- ps-clk-frequency = <33333333>;
fclk-enable = <0>;
clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x",
"cpu_1x", "ddr2x", "ddr3x",
--
2.3.5
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