On Wed, Jul 29, 2015 at 11:57:26AM +0000, Egli, Samuel wrote: > Hi James, > thank you for your reply! > > > -----Original Message----- > > From: Doublesin, James [mailto:[email protected]] > > Sent: Dienstag, 28. Juli 2015 21:59 > > To: Egli, Samuel; '[email protected]'; Balbi, Felipe > > Cc: '[email protected]'; '[email protected]'; 'Stefan Roese'; Meier, Roger; > > Senn, Joerg; Belogolov, Oleg > > Subject: RE: [RFC] am33xx: add 600us wait in DDR3 initialization sequence > > > > Hi Samuel, I don't think these changes are necessary. > > > > I think your concern about the initialization steps is not correct. The > > first setting of the REF_CTRL (before SDRAM_CONFIG write) will be used by > > the EMIF controller to determine the delay between the rising edge of > > DDR_RESETn and DDR_CKE. We typically write a value of 0x3100 in REF_CTRL > > to achieve this, which comes from this formula: > > > > (16*SDRAM_REF_CTRL)/400MHz > 500us > > That's interesting. This isn't really documented in the TRM. But I see > ddr.c: > ... > if (regs->zq_config) > writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl); > ... > Why does this depend on zq_config? While debugging I saw that we
This part I can answer. We use the same functions on DDR2 and DDR3 and use the presence of zq_config in regs to know if this is a DDR2 or DDR3 setup. -- Tom
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