On 07/08/2015 07:24 AM, Horia Geantă wrote:
> HW coherency won't work properly for CAAM write transactions
> if AWCACHE is left to default (POR) value - 4'b0001.
> It has to be programmed to 4'b0010.
>
> For platforms that have HW coherency support:
> -PPC-based: the update has no effect; CAAM coherency already works
> due to the IOMMU (PAMU) driver setting the correct memory coherency
> attributes
> -ARM-based: the update fixes cache coherency issues,
> since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
>
> Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
> Signed-off-by: Horia Geantă <horia.gea...@freescale.com>
> Reviewed-by: Aneesh Bansal <aneesh.ban...@freescale.com>
> Reviewed-by: Mingkai Hu <mingkai...@freescale.com>
> ---
Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks.
York
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