On Tuesday, August 04, 2015 at 11:04:38 PM, [email protected] wrote:
> From: Sylvain Lemieux <[email protected]>
>
> Incorporate DMA driver from legacy LPCLinux NXP BSP.
> The files taken from the legacy patch are:
> - lpc32xx DMA driver
> - lpc3250 header file DMA registers definition.
>
> The legacy driver was updated and clean-up as part of the integration with
> the latest u-boot.
>
> Signed-off-by: Sylvain Lemieux <[email protected]>
[...]
> +
> +/*
> + * The "dmac_ll" structure is mapping the DMA channel register,
> + * as per UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3
> + * tables 84, 85, 86 & 87.
> + *
> + * The DMA client (ex. NAND SLC) can use this macro to write the
> + * next DMA linked list item address.
> + */
> +#define lpc32xx_dmac_next_lli(x) (uint32_t)x
Ew, and it's not even used :-)
> +/* DMA linked list structure used with a channel's LLI register */
> +struct lpc32xx_dmac_ll {
> + u32 dma_src;
> + u32 dma_dest;
> + u32 next_lli;
> + u32 next_ctrl;
> +};
[...]
> +int lpc32xx_dma_wait_status(int channel)
> +{
> + unsigned long start;
> +
> + start = get_timer(0);
> + while (1) {
Here , you can do
reg = readl();
reg |= readl();
if (reg & BIT_MASK())
break;
> + if (((readl(&dma->raw_tc_stat) | readl(dma->raw_err_stat))
> + & BIT_MASK(channel)) != 0)
> + break;
> +
> + if (get_timer(start) > 10000)
> + return -1;
> +
> + udelay(1);
> + }
> +
> + if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {
> + setbits_le32(&dma->int_err_clear, BIT_MASK(channel));
> + setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));
> + return -1;
> + }
> + setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));
> + setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));
> + return 0;
> +}
Other than that,
Acked-by: Marek Vasut <[email protected]>
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