Hi Peng,
On 08/03/2015 01:06 PM, Peng Fan wrote:
The MIB RAM and FIFO receive start register does not exist on
i.MX6UL. Accessing these register will cause enet not work well.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Fugang Duan <[email protected]>
Cc: Joe Hershberger <[email protected]>
---
drivers/net/fec_mxc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index c5dcbbb..7fb1d5f 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -520,8 +520,10 @@ static int fec_open(struct eth_device *edev)
static int fec_init(struct eth_device *dev, bd_t* bd)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+#if !defined(CONFIG_MX6UL)
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
int i;
+#endif
/* Initialize MAC address */
fec_set_hwaddr(dev);
@@ -551,12 +553,14 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
writel(0x00000000, &fec->eth->gaddr2);
+#if !defined(CONFIG_MX6UL)
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
+#endif
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
Is it possible to do runtime check for the SoC type, instead of ifdefs?
Regards,
Nikolay
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