On Wed, Aug 12, 2015 at 08:22:13PM +0300, Vladimir Zapolskiy wrote: > LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones > and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit > wide. This means that if HCLK is 104MHz, then minimal configurable I2C > clock speed is about 51KHz. > > Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in > assumption that peripheral clock is 13MHz it allows to set the minimal > bus speed about 25.5KHz. > > Check for negative half clock value is removed since it is always false. > > The change fixes the following problem for I2C busses 0 and 1: > > => i2c dev 0 > Setting bus to 0 > => i2c speed 100000 > Setting bus speed to 100000 Hz > Failure changing bus speed (-22) > > Signed-off-by: Vladimir Zapolskiy <[email protected]> > Tested-by: Sylvain Lemieux <[email protected]>
Applied to u-boot/master, thanks! -- Tom
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