On Friday, August 21, 2015 at 07:00:46 AM, Chin Liang See wrote: > Hi, Hi,
> > > > > Any comment or ack for this patch? > > > > > > > > Please don't expect that the reviewers/maintainers have nothing else > > > > on their plate but to review your patch. Besides, this change is > > > > really low priority one, since thus far the SD/MMC works fine on all > > > > of the SoCFPGA boards to my knowledge. > > > > > > > > Also, I thought we agreed to wait for Simon to comment on this patch. > > > > You don't have to repost a patch before the discussion settles a bit. > > > > This doesn't help, it only puts burden on the receiving side, chill > > > > :) Let alone the fact that this code should be part of the DWMMC > > > > core, as it is not socfpga specific. > > > > > > > > What I would be really interested in is a proper description of the > > > > calibration algorithm. What is the goal and how do you achieve it ? > > > > > > Actually I am probing the efforts needed for this patch before moving > > > to next one. While for the SDMMC calibration, it is not needed if the > > > SD card is routed near to the chip. We have incident where SD access > > > failed as they routed few inches away. > > > > Does the calibration really help or is that a problem with the board ? > > It'd be nice if you put effort into this patch to get it done correctly > > :) > > It's related to the board. When the trace route is not properly design, > it might failed when communication between the controller and card at > high speed. The calibration will ensure the correct data being driven > and sampled at correct window. As this seems applicable for dwmmc, let > me take a look into other vendor implementation. Thanks again for the > advise :) OK Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot