On Thu, Aug 13, 2015 at 09:51:00AM -0500, Nishanth Menon wrote: > DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet > provided IODELAY values for standard RGMII phys do not work. > > Silicon Revision(SR) 2.0 provides an alternative bit configuration > that allows us to do a "gross adjustment" to launch the data off a > different internal clock edge. Manual IO Delay overrides are still > necessary to fine tune the clock-to-data delays. This is a necessary > workaround for the quirky ethernet Phy we have on the platform. > > NOTE: SMA registers are spare "kitchen sink" registers that does > contain bits for other workaround as necessary as well. Hence the > control for the same is introduced in a generic SoC specific, board > generic location. > > Signed-off-by: Nishanth Menon <[email protected]> > Reviewed-by: Tom Rini <[email protected]>
Applied to u-boot/master, thanks! -- Tom
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