With a working QSPI calibration, the SCLK can now run up to 100MHz Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Dinh Nguyen <dinh.li...@gmail.com> Cc: Marek Vasut <ma...@denx.de> Cc: Stefan Roese <s...@denx.de> Cc: Vikas Manocha <vikas.mano...@st.com> Cc: Jagannadh Teki <jt...@openedev.com> Cc: Pavel Machek <pa...@denx.de> Reviewed-by: Marek Vasut <ma...@denx.de> --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 9650eb0..04e5695 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -86,7 +86,7 @@ #size-cells = <1>; compatible = "n25q00"; reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + spi-max-frequency = <100000000>; m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ -- 1.7.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot