With a working QSPI calibration, the SCLK can now run up to 100MHz
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Vikas Manocha <[email protected]>
Cc: Jagannadh Teki <[email protected]>
Cc: Pavel Machek <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
---
arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 9650eb0..04e5695 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -86,7 +86,7 @@
#size-cells = <1>;
compatible = "n25q00";
reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ spi-max-frequency = <100000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
--
1.7.7.4
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