Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT
to get the corresponding bit mask per SoC (mx7 or mx6) to identify
if securue boot feature is enabled/disabled.
On authenticate_image only check for mmu enabled on mx6 SoC to
force pu_irom_mmu_enabled so ROM code can perform mmu cache flush
mx7 SoC ROM code does not have this issue as ROM enables cache support
based on fuse settings.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2:
- Split from original patch to track mx7 change set
hab: rework support for imx6/imx7
Changes for V3:
- Add helper macro to identify if secure boot is enabled per SoC family
(mx6/mx7)
- Improve commit log description
arch/arm/imx-common/hab.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index ee2da01..56b3c22 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -81,6 +81,8 @@
#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
+#define IS_HAB_ENABLED_BIT \
+ (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
/*
* +------------+ 0x0 (DDR_UIMAGE_START) -
@@ -273,7 +275,7 @@ bool is_hab_enabled(void)
return ret;
}
- return (reg & 0x2) == 0x2;
+ return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
}
static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
@@ -421,7 +423,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t
image_size)
* crash.
*/
/* Check MMU enabled */
- if (get_cr() & CR_M) {
+ if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
if (is_cpu_type(MXC_CPU_MX6Q) ||
is_cpu_type(MXC_CPU_MX6D)) {
/*
--
2.1.4
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