On 10/14/2015 04:44 AM, Gong Qianyu wrote: > From: Mingkai Hu <[email protected]> > > LSCH3 is a subclass of Freescale Layerscape.
You are preparing a new sub architecture. It would be better to explain the reason in the commit message. > > Signed-off-by: Mingkai Hu <[email protected]> > Signed-off-by: Gong Qianyu <[email protected]> > --- > V4: > - New patch. > > arch/arm/cpu/armv8/Makefile | 2 +- > .../armv8/{fsl-lsch3 => fsl-layerscape}/Makefile | 13 +- > .../README => fsl-layerscape/README.lsch3} | 0 > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.c | 146 ++++++++++------ > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.h | 2 +- > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/fdt.c | 17 +- > .../fsl_lsch3_serdes.c | 3 +- > .../speed.c => fsl-layerscape/fsl_lsch3_speed.c} | 3 +- > .../armv8/{fsl-lsch3 => fsl-layerscape}/lowlevel.S | 14 +- > .../{fsl-lsch3 => fsl-layerscape}/ls2085a_serdes.c | 3 +- > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/mp.c | 8 +- > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/soc.c | 35 +--- > arch/arm/cpu/armv8/fsl-layerscape/spl.c | 76 +++++++++ > arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 - > .../clock.h | 8 +- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 57 +++++++ > .../asm/arch-fsl-layerscape}/cpu.h | 3 + > .../{arch-fsl-lsch3 => arch-fsl-layerscape}/fdt.h | 4 + > .../fsl_serdes.h | 11 +- > .../immap_lsch3.h | 119 +++++++++++-- > .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 55 ++++++ > .../ls2085a_stream_id.h | 0 > arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 10 ++ > .../asm/arch-fsl-layerscape}/mp.h | 10 +- > .../{arch-fsl-lsch3 => arch-fsl-layerscape}/soc.h | 5 +- > arch/arm/include/asm/arch-fsl-layerscape/speed.h | 10 ++ > arch/arm/include/asm/arch-fsl-lsch3/config.h | 185 > --------------------- > arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 - > arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 -- > arch/arm/include/asm/config.h | 7 +- > arch/arm/include/asm/global_data.h | 2 +- > board/freescale/ls2085aqds/Kconfig | 2 +- > board/freescale/ls2085aqds/eth.c | 1 - > board/freescale/ls2085aqds/ls2085aqds.c | 2 +- > board/freescale/ls2085ardb/Kconfig | 2 +- > board/freescale/ls2085ardb/eth_ls2085rdb.c | 1 - > board/freescale/ls2085ardb/ls2085ardb.c | 2 +- > drivers/i2c/mxc_i2c.c | 4 +- > drivers/misc/fsl_debug_server.c | 1 - > drivers/net/ldpaa_eth/ls2085a.c | 2 - > drivers/pci/pcie_layerscape.c | 4 +- > include/common.h | 3 + > include/configs/ls2085a_common.h | 47 +++++- > 43 files changed, 540 insertions(+), 368 deletions(-) > > diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile > index adb11b3..48c041b 100644 > --- a/arch/arm/cpu/armv8/Makefile > +++ b/arch/arm/cpu/armv8/Makefile > @@ -15,6 +15,6 @@ obj-y += cache.o > obj-y += tlb.o > obj-y += transition.o > > -obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ > +obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ > obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ > obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ > diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile > b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > similarity index 56% > rename from arch/arm/cpu/armv8/fsl-lsch3/Makefile > rename to arch/arm/cpu/armv8/fsl-layerscape/Makefile > index 9f7815b..712917c 100644 > --- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > @@ -1,5 +1,5 @@ > # > -# Copyright 2014, Freescale Semiconductor > +# Copyright 2014-2015, Freescale Semiconductor > # > # SPDX-License-Identifier: GPL-2.0+ > # > @@ -7,7 +7,14 @@ > obj-y += cpu.o > obj-y += lowlevel.o > obj-y += soc.o > -obj-y += speed.o > -obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o > +ifneq ($(CONFIG_FSL_LSCH3),) > +obj-y += fsl_lsch3_speed.o > +endif What if CONFIG_FSL_LSCH3 is defined but empty? > + > obj-$(CONFIG_MP) += mp.o > obj-$(CONFIG_OF_LIBFDT) += fdt.o > +obj-$(CONFIG_SPL) += spl.o > + > +ifneq ($(CONFIG_LS2085A),) Same here <snip> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > new file mode 100644 > index 0000000..27d4582 > --- /dev/null > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -0,0 +1,57 @@ > +/* > + * Copyright 2015, Freescale Semiconductor > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ > +#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ > + > +#include <fsl_ddrc_version.h> > + > +#if defined(CONFIG_LS2085A) > +#define CONFIG_MAX_CPUS 16 > +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 > +#define CONFIG_NUM_DDR_CONTROLLERS 3 > +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } > +#define SRDS_MAX_LANES 8 > +#define CONFIG_SYS_FSL_SRDS_1 > +#define CONFIG_SYS_FSL_SRDS_2 > +#define CONFIG_SYS_PAGE_SIZE 0x10000 > +#define CONFIG_SYS_CACHELINE_SIZE 64 > +#ifndef L1_CACHE_BYTES > +#define L1_CACHE_SHIFT 6 > +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) > +#endif > + > +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ > +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ > + > +/* DDR */ > +#define CONFIG_SYS_FSL_DDR_LE > +#ifdef CONFIG_SYS_FSL_DDR4 > +#define CONFIG_SYS_FSL_DDRC_GEN4 > +#else > +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ > +#endif > +#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ > +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) > +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE Some non-soc specific macros can be moved out of #ifdef. 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