On Wednesday, October 14, 2015 at 06:32:42 PM, Pavel Machek wrote: > On Mon 2015-10-12 09:59:57, [email protected] wrote: > > From: Dinh Nguyen <[email protected]> > > > > Update the L2 AUX CTRL settings for the SoCFPGA. > > > > Enabling D and I prefetch bits helps improve SDRAM performance on the > > platform. > > > > Also, we need to enable bit 22 of the L2. By not having bit 22 set in the > > PL310 Auxiliary Control register (shared attribute override enable) has > > the side effect of transforming Normal Shared Non-cacheable reads into > > Cacheable no-allocate reads. > > > > Coherent DMA buffers in Linux always have a Cacheable alias via the > > kernel linear mapping and the processor can speculatively load cache > > lines into the PL310 controller. With bit 22 cleared, Non-cacheable > > reads would unexpectedly hit such cache lines leading to buffer > > corruption. > > > > Signed-off-by: Dinh Nguyen <[email protected]> > > --- > > > > arch/arm/include/asm/pl310.h | 2 ++ > > arch/arm/mach-socfpga/misc.c | 12 ++++++++++++ > > 2 files changed, 14 insertions(+) > > > > diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h > > index 18b90b7..7a11405 100644 > > --- a/arch/arm/include/asm/pl310.h > > +++ b/arch/arm/include/asm/pl310.h > > @@ -17,6 +17,8 @@ > > > > #define L2X0_CTRL_EN 1 > > > > #define PL310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) > > > > +#define PL310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) > > +#define PL310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) > > These would be > > arch/arm/include/asm/hardware/cache-l2x0.h:#define > L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) > arch/arm/include/asm/hardware/cache-l2x0.h:#define > L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29) > > ...in kernel. So maybe staying with L310_ prefix makes sense? > Otherwise it looks ok.
Why is it L... in one and PL... in the other one ? What does the "PL" prefix stand for anyway ? Best regards, Marek Vasut _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
