Penda, Naveen Kumar wrote: > From: Penda Naveen Kumar<[email protected]> > > This patch provides bug fix, when omap3 uses nor boot. > > Signed-off-by: Penda Naveen Kumar<[email protected]>
Makes sense! Most probably not found earlier because most OMAP3 boards have no NOR. Acked-by: Dirk Behme <[email protected]> > Index: u-boot/cpu/arm_cortexa8/omap3/lowlevel_init.S > =================================================================== > --- u-boot.orig/cpu/arm_cortexa8/omap3/lowlevel_init.S > +++ u-boot/cpu/arm_cortexa8/omap3/lowlevel_init.S > @@ -135,19 +135,19 @@ _go_to_speed: .word go_to_speed > /* these constants need to be close for PIC code */ > /* The Nor has to be in the Flash Base CS0 for this condition to happen */ > flash_cfg1_addr: > - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) > + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) > flash_cfg3_addr: > - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) > + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) > flash_cfg3_val: > .word STNOR_GPMC_CONFIG3 > flash_cfg4_addr: > - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) > + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) > flash_cfg4_val: > .word STNOR_GPMC_CONFIG4 > flash_cfg5_val: > .word STNOR_GPMC_CONFIG5 > flash_cfg5_addr: > - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) > + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) > pll_ctl_add: > .word CM_CLKEN_PLL > pll_div_add1: > _______________________________________________ > U-Boot mailing list > [email protected] > http://lists.denx.de/mailman/listinfo/u-boot > _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
