+
+struct ath79_spi_priv {
+ void __iomem *regs;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ return readl(priv->regs + offset);
+}
+
+static inline void ath79_spi_write(struct udevice *bus,
+ u32 val, u32 offset)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ writel(val, priv->regs + offset);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ uint8_t *rx = din;
+ const uint8_t *tx = dout;
+ uint8_t curbyte, curbitlen, restbits;
+ uint32_t bytes = bitlen / 8;
+ uint32_t out;
+ uint32_t in;
+
+ if (flags & SPI_XFER_BEGIN) {
+ ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+ ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+ }
+
+ restbits = (bitlen % 8);
+ if (restbits)
+ bytes++;
+
+ /* enable chip select */
+ out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+ while (bytes--) {
+ curbyte = 0;
+ if (tx)
+ curbyte = *tx++;
+
+ if (restbits) {
+ curbitlen = restbits;
+ curbyte <<= 8 - restbits;
+ } else {
+ curbitlen = 8;
+ }
+
+ /* clock starts at inactive polarity */
+ for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+ if (curbyte & 0x80)
+ out |= AR71XX_SPI_IOC_DO;
+ else
+ out &= ~(AR71XX_SPI_IOC_DO);
+
+ /* setup MSB (to slave) on trailing edge */
+ ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
+ ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
+ AR71XX_SPI_REG_IOC);
+ curbyte <<= 1;
+ }
+
+ in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
+ if (rx) {
+ if (restbits)
+ *rx++ = (in << (8 - restbits));
+ else
+ *rx++ = in;
+ }
+ }
+
+ if (flags & SPI_XFER_END) {
+ ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
+ AR71XX_SPI_REG_IOC);
+ ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+ ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+ }
+
+ return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+ u32 val, div = 0;
+
+ if (speed)
+ div = get_bus_freq(0) / speed;
+
+ if (div > 63)
+ div = 63;
+
+ if (div < 5)
+ div = 5;
+
+ ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+ val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL);
+ val &= ~AR71XX_SPI_CTRL_DIV_MASK;
+ val |= SPI_CLK_DIV(div);
+ ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL);
+ ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+ return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ struct ath79_spi_platdata *plat = dev_get_platdata(bus);
+
+ priv->regs = plat->regs;
+
+ /* Init SPI Hardware, disable remap, set clock */
+ ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+ ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8),
+ AR71XX_SPI_REG_CTRL);
+ ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+
+ return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ /* Always allow activity on CS 0/1/2 */
+ if (cs >= 3)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int ath79_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct ath79_spi_platdata *plat = dev_get_platdata(bus);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->regs = map_physmem(addr,
+ AR71XX_SPI_SIZE,
+ MAP_NOCACHE);
