Hi Fabio, On Tue, Jan 5, 2016 at 1:02 PM, Fabio Estevam <[email protected]> wrote: > From: Fabio Estevam <[email protected]> > > As per the AR8031 datasheet: > > "For a reliable power on reset, suggest to keep asserting the reset > low long enough (10ms) to ensure the clock is stable and clock-to-reset > 1ms requirement is satisfied." > > So do as suggested and also add a 100us delay after deasserting the > reset line to guarantee that the PHY ID can be read correctly and the > Atheros 8031 PHY driver can be loaded automatically. > > This results in a simpler code. > > Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Joe Hershberger <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
