Hi Stefan, On Mon, Jan 18, 2016 at 1:44 AM, Stefan Roese <[email protected]> wrote: > Hi Bin, > > On 17.01.2016 03:35, Stefan Roese wrote: >> >> On 16.01.2016 15:08, Bin Meng wrote: >>> >>> On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese <[email protected]> wrote: >>>> >>>> Hi Simon, Hi Bin! >>>> >>>> I'm currently busy with porting U-Boot to a Bay Trail board. >>>> Equipped with an Intel Atom E3845 and additionally the >>>> Nuvoton / Winbond W83627DHG Super IO chip. >>>> >>>> My staring point for this port is the Minnowboard MAX, which >>>> works very well btw. I've used the same binaries as described >>>> in the README.x86 as on the MinnowMAX for this new Bay Trail >>>> board. But am not able yet to see any output on the DEBUG_UART. >>>> >>>> Bin, you already mentioned in a previous mail, that I need to >>>> enable the legacy UART in the Super IO chip for this. I've >>>> started adding a small driver for this, similar to the one >>>> you've introduced for the SMSC: >>> >>> >>> Ah, looks I delivered inaccurate information before! I just remember >>> BayTrail SoC integrates a legacy UART at I/O 0x3f8 and it is enabled >>> by FSP by default. If you use a debug version of FSP (only gold4 >>> release provides a debug version FSP), you will se lots of useful >>> debug information printed on the serial port (the one connected to the >>> SoC legacy UART). But, why does your board have an additional Nuvoton >>> / Winbond W83627DHG Super IO chip? I guess it's for other legacy >>> peripherals like 8042 KBC, etc? We need figure out the serial port you >>> are trying to enable is connected to which chip. If it is connected >>> directly to BayTrail SoC, then you don't need program this W83627DHG. >> >> >> It is connected to the Winbond UART. So we need to enable and use it. >> But how can I disable the BayTrail internal legacy UART? So that the >> Winbond one is really used? > > > Okay. I was able to work around this problem with the included > legacy UART in the Bay Trail Atom. By moving the IO base address > of the Winbond COM1 from 0x3f8 to a different (unused) location. > And then using this new address as the UART base address. U-Boot > boots to the prompt with the "fixed" memory-down DDR parameters > to the FSP in this configuration.
This is great! > > Still I would really like to disable the internal legacy UART > and only use the Winbond UART(s) at the default address. Disabling > the Bay Trail legacy UART by clearing the "UART_CONT.COM1EN" bit, > as described in the "Intel AtomTM Processor E3800 Product Family > Datasheet", does not seem to fix this problem. I need to double > check this tomorrow though. > > Bin, Simon, do you have any ideas on how to disable this Atom > legacy UART instead. It must be possible, as when booting into > Linux with the original BIOS, the Winbond COM1 works just fine > at 0x3f8. > I checked FSP VPD of BayTrial, looks Intel does not expose a config option to enable/disable the legacy UART integrated into the SoC, neither an option to move its I/O address, instead it enables the legacy UART always and has a fixed address 0x3f8. Per my understanding of the datasheet, I think you are right, "UART_CONT.COM1EN" bit should be the key to enable/disable the legacy UART. But I suspect FSP turns it on again during every call to the FSP API (like fsp_init(), fsp_notify()). You may try: after each call to fsp_init() and fsp_notify(), try adding the codes to turn off the "UART_CONT.COM1EN" bit and see what's going on there. Regards, Bin _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
