On Tuesday, January 26, 2016 at 05:40:49 PM, Albert ARIBAUD wrote: > Some armv7 targets are missing a cache line size declaration. > In preparation for "arm: cache: Implement cache range check for v7" > patch, add these declarations with the appropriate value for > the target's SoC or CPU. > > Signed-off-by: Albert ARIBAUD <albert.u.b...@aribaud.net>
[...] > diff --git a/include/configs/at91-sama5_common.h > b/include/configs/at91-sama5_common.h index 9db4a4f..7b06601 100644 > --- a/include/configs/at91-sama5_common.h > +++ b/include/configs/at91-sama5_common.h > @@ -12,6 +12,8 @@ > > #include <asm/hardware.h> > > +#define CONFIG_SYS_CACHELINE_SIZE 64 > + > #define CONFIG_SYS_TEXT_BASE 0x26f00000 > > /* ARM asynchronous clock */ I think SAMA5 is CortexA5 and that has 32B cachelines. Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
