On 01/05/2016 07:34 PM, Shengzhou Liu wrote: > During the receive data training, the DDRC may complete on a > non-optimal setting that could lead to data corruption or > initialization failure. > > Workaround: before setting MEM_EN, set DEBUG_29 register with > specific value for different data rates. > > Signed-off-by: Shengzhou Liu <[email protected]> > --- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + > drivers/ddr/fsl/fsl_ddr_gen4.c | 18 ++++++++++++++++++ > 2 files changed, 19 insertions(+) >
Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks. York _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
