Thanks for the info.
On Tue, Sep 1, 2009 at 10:33 AM, Paulraj, Sandeep <s-paul...@ti.com> wrote:
> This patch is fine.
>
> I'll send an updated NAND Davinci driver patch soon which adds to what is
> already there. I have made a mistake and testing did not show it.
>
> Have you noticed that not all e-mails reach the mailing list in the correct
> order? This is true for the conversation you two were having.
>
> Thanks,
> Sandeep
>
> > -----Original Message-----
> > From: Paulraj, Sandeep
> > Sent: Tuesday, September 01, 2009 12:04 PM
> > To: Scott Wood; John Rigby
> > Cc: u-boot@lists.denx.de; Paulraj, Sandeep; Narnakaje, Snehaprabha
> > Subject: RE: [U-Boot] [PATCH 2/2] MTD:NAND: ADD new ECC mode
> > NAND_ECC_HW_OOB_FIRST
> >
> >
> > > John Rigby wrote:
> > > > Sorry for the late comments. We have been trying to use this code
> > with
> > > > the associated davinci 4-bit ecc patches and have some questions
> > We use this internally and it works. Are you having any issues because we
> > don't see any!!
> > J-C has to apply a patch and you will need that for this to work
> properly.
> > That patch updates the DM355 Config
> > > (inline).
> > > >
> > > > .....
> > > > + uint8_t *ecc_code = chip->buffers->ecccode;
> > > > + uint32_t *eccpos = chip->ecc.layout->eccpos;
> > > > + uint8_t *ecc_calc = chip->buffers->ecccalc;
> > > > +
> > > > + /* Read the OOB area first */
> > > > + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
> > > >
> > > >
> > > > What about chips that do not support the NAND_CMD_READOOB? Do I
> need
> > > > to provide my own read routine for that case?
> > >
> > > cmdfunc is supposed to fix that up. This is already the case with
> > > existing code.
> > >
> > > > + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
> > > > + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
> > > > +
> > > > + for (i = 0; i < chip->ecc.total; i++)
> > > > + ecc_code[i] = chip->oob_poi[eccpos[i]];
> > > > +
> > > > + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p +=
> > > eccsize) {
> > > > + int stat;
> > > > +
> > > > + chip->ecc.hwctl(mtd, NAND_ECC_READ);
> > > > + chip->read_buf(mtd, p, eccsize);
> > > > + chip->ecc.calculate(mtd, p, &ecc_calc[i]);
> > > >
> > > >
> > > > Here you calculate ecc then never use the result?
> > >
> > > Hmm, that looks wrong, both here and in the davinci driver. Are the
> two
> > > calls to nand_davinci_4bit_readecc reading different things? Does the
> > > calculate function have any side effects beyond producing data that is
> > > never used?
> > Have you reads the patch description. Maybe that might help a bit
> >
> > This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to
> > support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND
> > chips. This ECC mode is similar to NAND_ECC_HW, with the exception of
> > read_page API that first reads the OOB area, reads the data in chunks,
> > feeds the ECC from OOB area to the ECC hw engine and perform any
> > correction on the data as per the ECC status reported by the engine.
> >
> > >
> > > -Scott
> > > _______________________________________________
> > > U-Boot mailing list
> > > U-Boot@lists.denx.de
> > > http://lists.denx.de/mailman/listinfo/u-boot
>
>
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