Am 04.04.2016 um 09:32 schrieb Alexander Graf: > The cache line flush helpers only work properly when they get aligned > start and end addresses. Round our flush range to cache line size. It's > safe because we're guaranteed to flush within a single page which has the > same cache attributes. > > Reported-by: Marek Vasut <ma...@denx.de> > Signed-off-by: Alexander Graf <ag...@suse.de> > --- > lib/efi_loader/efi_runtime.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c > index 22bcd08..40acec0 100644 > --- a/lib/efi_loader/efi_runtime.c > +++ b/lib/efi_loader/efi_runtime.c > @@ -194,7 +194,8 @@ void efi_runtime_relocate(ulong offset, struct > efi_mem_desc *map) > #endif > > *p = newaddr; > - flush_dcache_range((ulong)p, (ulong)&p[1]); > + flush_dcache_range((ulong)p & ~(CONFIG_SYS_CACHELINE_SIZE - 1), > + ALIGN((ulong)&p[1], CONFIG_SYS_CACHELINE_SIZE));
dragonboard410c_defconfig fails to build with this due to undefined CONFIG_SYS_CACHELINE_SIZE. Do we need to #ifdef here or is the dragonboard410c at fault for not defining it? jetson-tk1_defconfig for instance builds fine with this patch. Regards, Andreas > } > > #ifndef IS_RELA -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot